Dr. Prince Kumar Singh

Assistant Professor (Contract)
Displaying 1 - 41 of 41 publications

2021

  1. Manas Ranjan Tripathy , A. Samad , Ashish Kumar Singh , Prince Kumar Singh, Kamalaksha Baral, Ashwini Kumar Mishra, Satyabrata Jit Impact of interface trap charges on electrical performance characteristics of a source pocket engineered Ge/Si heterojunction vertical TFET with HfO2/Al2O3 laterally stacked gate oxide, Microelectronics Reliability, Elsevier , 2021, Impact Factor : 1.535
  2. Kamalaksha Baral , Prince Kumar Singh , Gautam Kumar , Ashish Kumar Singh, Manas Ranjan Tripathy, Sanjay Kumar, Satyabrata Jit Impact of ion implantation on stacked oxide cylindrical gate junctionless accumulation mode MOSFET: An electrical and circuit level analysis, Materials Science in Semiconductor Processing , Elsevier , 2021, Impact Factor : 3.085

2020

  1. Prince Kumar Singh , Kamalaksha Baral , Sanjay Kumar , Sweta Chander, Manas Ranjan Tripathy, Ashish Kumar Singh & Satyabrata Jit Source pocket engineered underlap stacked oxide cylindrical gate tunnel FETs with improved performance: design and analysis, Applide Physics A , Springer , 2020, Impact Factor : 1.810
  2. Ashish Kumar Singh , Manas Ranjan Tripathy , Kamalaksha Baral, , Prince Kumar Singh, and Satyabrata Jit DC, RF and linearity analyses of a back-gated (BG) heterojunction (HJ) TFET-on-SELBOX-substrate (STFET): Introduction to a BG-HJ-STEFT based CMOS inverter, Microelectronics Journal, Elsevier, 2020, Impact Factor : 1.8
  3. Prince Kumar Singh , Kamalaksha Baral , Sanjay Kumar , Ashish Kumar Singh, Manas Ranjan Tripathy, Rishibrind Kumar Upadhyay and Satyabrata Jit Subthreshold Swing Modeling of Gaussian Doped Double-Gate MOSFETs and its Validation Based on TCAD Simulation, CONECCT-2020, IEEE, 2020,
  4. Prince Kumar Singh , Kamalaksha Baral , Sanjay Kumar , Manas Ranjan Tripathy, Ashish Kumar Singh, Rishibrind Kumar Upadhyay, Sweta Chander & Satyabrata Jit Analytical Drain Current Model for Source Pocket Engineered Stacked Oxide SiO2/HfO2 Cylindrical Gate TFETs, Silicon , Springer , 2020, Impact Factor : 1.499
  5. Ashish Kumar Singh , Manas Ranjan Tripathy , Kamalaksha Baral, , Prince Kumar Singh, and Satyabrata Jit Impact of interface trap charges on device level performances of a lateral/vertical gate stacked Ge/Si TFET-on-SELBOX-substrate, Appl. Phys A, Springer, 2020, Impact Factor : 1.810
  6. Prince Kumar Singh , Kamalaksha Baral , Ashish Kumar Singh , Manas Ranjan Tripathy, Rishibrind Kumar Upadhyay, Abhinav Pratap Singh, Satyabrata Jit Influence of Temperature on Analog/Radio Frequency Appearances of Heterojunction Cylindrical Gate Tunnel FETs, GUCON-2020 , IEEE , 2020,
  7. Ashish Kumar Singh , Manas Ranjan Tripathy, , Prince Kumar Singh , Kamalaksha Baral, Sweta Chander, and Satyabrata Jit Deep Insight into DC/RF and Linearity Parameters of a Novel Back Gated Ferroelectric TFET on SELBOX Substrate for Ultra Low Power Applications, 2020, Springer, 2020, Impact Factor : 1.405
  8. Manas Ranjan Tripathy , Ashish Kumar Singh , Kamalaksha Baral , Prince Kumar Singh, Ashwini Kumar Mishra, and Satyabrata Jit Study of Temperature Sensitivity on Linearity Figures of Merit of Ge/Si Hetero-Junction Gate-Drain Underlapped Vertical Tunnel FET with heterogeneous gate dielectric structure for Improving Device Reliability," on Radio Science, URSI Regional Conference, URSI-RCRS, 2020,
  9. Kamalaksha Baral , Prince Kumar Singh , Sanjay Kumar , Ashish Singh, Manas Tripathy, Sweta Chander, and Satyabrata Jit A 2-D compact DC model for engineered nanowire JAM-MOSFETs valid for all operating regimes, SST, IOP-Science, 2020, Impact Factor : 2.36`
  10. Ashish Kumar Singh , Manas Ranjan Tripathy , Kamalaksha Baral , Prince Kumar Singh, and Satyabrata Jit Design and Investigation of Lateral HfO2/SiO2 Gate Stacked TFET on SELBOX Substrate for Low Power and High-Frequency Applications, URSI-RCRS, URSI-RCRS, 2020,
  11. Manas Ranjan Tripathy , Ashish Kumar Singh , Kamalaksha Baral , Prince Kumar Singh, and Satyabrata Jit III-V/Si staggered heterojunction based source-pocket engineered vertical TFETs for low power applications, Superlattices and Microstructures , Elsevier , 2020, Impact Factor : 2.120
  12. Rishibrinda Kumar Upadhyay , Abhinav Pratap Singh , Deep Chandra Upadhyay , Prince Kumar Singh,Ashish Kumar Singh, and S. Jit ITO/ZnO/CH3NH3PbI3/Ag Hetro-Structure based Photodetector, GUCON, IEEE , 2020,
  13. Manas Ranjan Tripathy , Ashish Kumar Singh , Sweta Chander , Prince Kumar Singh, Kamalaksha Baral, and Satyabrata Jit Device-Level Performance Comparison of Some Pocket Engineered III-V/Si Hetero-Junction Vertical Tunnel Field Effect Transistor, ICDCS, IEEE, 2020,
  14. Manas Ranjan Tripathy , Ashish Kumar Singh , A.Shamad , Prince Kumar Singh, Kamalaksha Baral, and Satyabrata Jit, Impact of heterogeneous gate dielectric on DC, RF and circuit-level performance of source-pocket engineered Ge/Si heterojunction vertical TFET, Semiconductor Science and Technology, IOP-Science , 2020, Impact Factor : 2.361
  15. Manas Ranjan Tripathy , Ashish Kumar Singh , A Shamad , Kamalaksha Baral, Prince Kumar Singh, and Satyabrata Jit, Performnce comparison of Ge/Si Hetero-Junction Vertical Tunnel Fet with and without Gate-Drain Underlapped structure with application to Digital Inverter, EDTM-2020, IEEE, 2020,
  16. Sanjay Kumar , Kunal Singh , Kamalaksha Baral , Prince Kumar Singh, and Satyabrata Jit 2-D Analytical Model for Electrical Characteristics of Dual Metal Heterogeneous Gate Dielectric Double-Gate TFETs with Localized Interface Charges, Silicon , Springer , 2020, Impact Factor : 1.499
  17. Ashish Kumar Singh , Manas Ranjan Tripathy , Kamalaksha Baral , Prince Kumar Singh, and Satyabrata Jit Feroelectric Gate Heterojunction TFET on Selective Burried Oxide (SELBOX) Substrate for Distortionless and Low Power Application, EDTM, IEEE, 2020, DOI : 10.1109/EDTM47692.2020.9117858
  18. Kamalaksha Baral , Prince Kumar Singh , Sanjay Kumar , Ashish Singh, Manas Tripathy, Sweta Chander, and Satyabrata Jit 2-D analytical modeling of drain and gate-leackage current of cylindrical gate asymmetric halo doped dual material-junction less accumulation mode MOSFET, International Journal of Electronics and Communications, Springer, 2020, Impact Factor : 2.924
  19. Manas Ranjan Tripathy , Ashish Kumar Singh , A.Shamad , Sweta Chander, Kamalaksha Baral, Prince Kumar Singh, and Satyabrata Jit Device and Circuit level assessment of GaSb/Si Hetrojunction Vertical Tunnel-FET for Low-Power Application, IEEE Transactions on Electron Devices , IEEE , 2020, Impact Factor : 2.704

2019

  1. Prince Kumar Singh , Kamalaksha Baral , Sweta Chander , Sanjay Kumar, Manas Ranjan Tripathy, Ashish Kumar Singh, and Satyabrata Jit Impact of Gate Dielectrics on Analog/RF Performance of Double Gate Tunnel Field Effect Transistor, IEMENTech-2019, IEEE, 2019,
  2. Kamalaksha Baral , Prince Kumar Singh , Sanjay Kumar , Sweta Chander, Manas Ranjan Tripathy, and S. Jit Dual Material-Stacked Hetero-Dielectric-Junctionless Accumulation Mode Nanotube MOSFET for enhanced Hot Carrier and Trapped Charges Reliability, EDTM, IEEE, 2019,
  3. Ashish Kumar Singh , Dhruva jyoti Barah , Manas Ranjan Tripathy , Kamalaksha Baral, Sweta Chander, Prince Kumar Singh, and Satyabrata Jit Study and Investigation of DC and RF Performance of TFET on SEL-BOX and Conventional SOI TFET with SiO2 /HfO2 Stacked Gate Structure, IEMENTech, IEEE, 2019,
  4. Manas Ranjan Tripathy , Ashish Kumar Singh , A Shamad , Sweta Chander, Prince Kumar Singh, Kamalaksha Baral, Ashwini Kumar Mishra, and Satyabrata Jit Performance investigation of p-Channel Hetero–Junction GaN Tunnel FET, IMARC, IEEE, 2019,
  5. Sweta Chander , S. Baishya , sanjeet Kumar Sinha , Sanjay Kumar, Prince Kumar Singh, Kamlaksha Baral, Manas Ranjan Tripathy, Ashish Kumar Singh , and Satyabrata Jit Two-diemensional analytical modeling for electrical characteristics of Ge/Si SOI-tunnel FinFETs, Superlattices and Microstructures , Elsevier , 2019, DOI : 2.12
  6. Ashish Kumar Singh , Manas Ranjan Tripathy , Sweta Chander , Kamalaksha Baral, Prince Kumar Singh, and Satyabrata Jit Simulation Study and Comparative Analysis of Some TFET Structures with a Novel Partial-Ground-Plane (PGP) Based TFET on SELBOX Structure, Silicon, Springer Journals Publication, 2019, Impact Factor : 1.407
  7. Kamalaksha Baral , Prince Kumar Singh , Sanjay Kumar , Sweta Chander, and Satyabrata Jit Ultrathin Body Nanowire Hetero-dielectric Stacked Asymmetric Halo Doped Junction less Accumulation Mode MOSFET for Enhanced Electrical Characteristics and Negative Bias Stability, Superlattices and Microstructures, Elsevier , 2019, Impact Factor : 2.120
  8. Prince Kumar Singh , Kamalaksha Baral , Sanjay Kumar , S Chander & S Jit Analytical drain current model of stacked oxide SiO2/HfO2 cylindrical gate tunnel FETs with oxide interface charge, INJP , Springer Journals Publication , 2019, Impact Factor : 1.49

2018

  1. Sanjay Kumar , Prince Kumar Singh , Sweta Chander , Ashvini Rahangdale, Kamalaksha Baral, and Satyabrata Jit Dual-Material Ferroelectric Stacked Gate SiO2/PZT SOI Tunnel FETs with Improved Performance: Design and Analysis, SPIN, IEEE, 2018,
  2. Kamalaksha Baral , Prince Kumar Singh , Sweta Chander , Kunal Singh , and S. Jit Performance Analysis of Nanotube Junctionless Accumulation Mode MOSFETs with Ion Implanted Doping Profile, I2CT-2018, IEEE, 2018,
  3. Sanjay Kumar , Kamalaksha Baral , Sweta Chander , Prince Kumar Singh, Kunal Singh, and Satyabrata Jit Influence of Localized Interface Charges on Drain Current of Dual-Material Double-Gate Tunnel FETs, I2CT , IEEEE , 2018,
  4. Sanjay Kumar , Kamalaksha Baral , Sweta Chander , Prince Kumar Singh, Balraj Singh, and Satyabrata Jit Performance evaluation of double gate III-V heterojunction tunnel FETs with SiO2/HfO2 Gate oxide structure, ISDCS, IEEE, 2018,

2017

  1. Sanjay Kumar , Ekta Goel , Kunal Singh , Balraj Singh, Prince Kumar Singh, Kamalaksha Baral and Satyabrata Jit 2-D Analytical Modeling of the Electrical Characteristics of Dual-Material DG TFETs with a SiO2/High-k Stacked Gate-Oxide Structure, IEEE Transaction on Electronics Devices , IEEE , 2017, Impact Factor : 2.704
  2. Kamalaksha Baral , Prince Kumar Singh , Sanjay Kumar , Sweta Chander, and S. Jit Performance Analysis and Optimization of Nanotube Junctionless Accumulation MOSFETs with Lateral HfO2/SiO2 Gate-oxide Structure, NANOfIM, IEEE, 2017,
  3. Sanjay Kumar , Kunal Singh , Sweta Chander , Ekta Goel, Balraj Singh, Prince Kumar Singh, Kamalaksha Baral and Satyabrata Jit 2-D Analytical Drain Current Model of Heterojunction DG TFETs with a SiO2/High-k Stacked Gate-Oxide Structure, IEEE Transactions on Electron Devices , IEEE , 2017, Impact Factor : 2.704
  4. Sanjay Kumar , Ashvini Rahangdale , Sweta Chander , Prince Kumar Singh, Kamalaksha Baral, and Satyabrata Jit A Simulation Based Study for Electrical Characteristics of SOI TFETs With Ferroelectric Stacked Gate Oxide Structure, INDICON, IEEE, 2017,
  5. Kunal Singh , Sanjay Kumar , Ekta Goel , Balraj Singh, Prince Kumar Singh, Kamalaksha Baral, Hemant Kumar, and Satyabrata Jit, Effects of source/drain elevation and side spacer dielectric on drivability performance of non-abrupt ultra shallow junction gate underlap GAA MOSFETs, INJP, Springer Journals Publication , 2017, Impact Factor : 1.407
  6. Sweta Chander , Sanjeet Kumar Sinha, , Sanjay Kumar , Prince Kumar Singh, Kamlaksha Baral, Kunal Singh, and Satyabrata Jit Temperature Analysis of Ge/Si Heterojunction SOI-Tunnel FET, Superlattices and Microstructures , Springer , 2017, Impact Factor : 2.120
  7. Sweta Chander , Sanjeet Kumar Sinha , Sanjay Kumar , Prince Kumar Singh, Kamalaksha Baral, and S. Jit, Performance evalution of heterojunction SOI-Tunnel FET with temperture, INDICON, IEEE, 2017,
  8. Prince Kumar Singh , Sanjay Kumar , Sweta Chander , Kamalaksha Baral, and Satyabrata Jit Impact of Strain on Electrical Characteristic of Double-Gate TFETs with a SiO2/HfO2 Stacked Gate-Oxide Structure, INDICON-2017, IIT Roorkee, 2017,
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International

  1. Virtual Symposium on Recent Technological Advancement in Wide/Ultra-Wide Bandgap Semiconductor Materials,Device,and… - BITS PILANI Attendee
  2. International Conference on Advansed Computing and Inteligent Technologies(ICACIT)) - Galgotias University and Universita Di Siena Italy Attendee
  3. Next-Generation Nano-electronics Devices, Circuits and its Applications using EDA tools - IIIT Bhagalpur Attendee
  4. International Conference on Emerging Electronics (IEEE-ICEE-2020) - IIT Delhi Author