Dr. Subodh Wairya

Professor
Regular
Electronics & Communication Engineering Department
[email protected]
Dean Student Welfare
Chief Warden (Male) +
Displaying 1 - 26 of 26
Book Chapter

2023

  1. A Comparative Performance Analysis of QCA Full Adder”, International Conference on Intelligent Systems and Smart Infrastructure (ICISSI 2022), Ayushi Kirti Singh , Subodh Wairya , Divya Tripathi, 9 pages, CRC Press, Taylor & Francis Group, , 2023, ISBN : 978-1-032-41287-0,
  2. Design and Analysis of High speed and Low Power Dynamic Comparator”, 1st International Conference on Intelligent Systems and Smart Infrastructure (ICISSI 2022), Kunal Kumar , Anurag Yadav , Subodh Wairya, 11 pages, CRC Press, Taylor & Francis Group, , 2023, ISBN : 978-1-032-41287-0,
  3. Performance analysis of various fast and low power dynamic comparators, Intelligent Systems and Smart Infrastructure: Proceedings of ICISSI 202, Nashra Khalid , Anurag Yadav , Subodh Wairya, 9 pages, CRC Press, Taylor & Francis Group, , 2023, ISBN : 978-1-032-41287-,0,
  4. Saqib, M., Wairya, S., Yadav, A. (2023). Performance Analysis of Differential Dual Stage Delay Cells of VCO. VLSI, Communication and Signal Processing. VCAS 2022. Lecture Notes in E, Mohd Saqib , Subodh Wairya , Anurag Yadav, 15 pages, Springer Nature Singapore , 2023, ISBN : 978-981-99-0973-5,
  5. Design of Ultralow-Power and High-Speed Comparator Using Charge Sharing Technique. VLSI, Communication and Signal Processing. VCAS 2022. Lecture Notes in Electrical Engineering, vol 1024. Springer, Singapore., Kunal Kumar , Anurag Yadav , Subodh Wairya, 18 pages, Springer, Singapore , 2023, ISBN : 978-981-99-0973-5,
  6. Cell Optimization and Realization of XOR-Based Logic Design in QCA, VLSI, Communication and Signal Processing. VCAS 2022. Lecture Notes in Electrical Engineering, vol 1024. Springer, Singapore., Ayushi Kirti Singh , Subodh Wairya , Divya Tripathi, 30 pages, Springer Nature Singapore , 2023, ISBN : 978-981-99-0973-5,

2022

  1. Performance Evaluation of Master–Slave D Flip Flop Based on Charge Retention Feedback Pass Transistor Logic in Nanotechnology Recent Trends in Electronics and Communication. Lecture Notes in Electrical Engineering, vol 777. pp405-424, Sweta Tripathi , Anum Khan , Subodh Wairya, 18 pages, Springer, Singapore , 2022, ISBN : 978-981-16-2761-3,
  2. An Ultra Efficient QCA SRAM Cell for Nanotechnology Applications, Lect. Notes Electrical Eng., Vol. 911, Amit Dhawan et al. (Eds): Advances in VLSI, Communication, and Signal Processing, Divya Tripathi , Subodh Wairya , 11 pages, Springer, Singapore , 2022, ,
  3. Performance Estimation of Different Tunnel Field Effect Transistor Based Biosensors used in the Biomedical and its Future Prospective, Lect. Notes Electrical Eng., Vol. 911, Amit Dhawan et al. (Eds): Advances in VLSI, , Shilpi Gupta , Subodh Wairya , 11 pages, Springer, Singapore , 2022, ,
  4. Performance Analysis of Vedic multiplier using High Performance XOR-MUX based adder for Fast Computation”, Lect. Notes Electrical Eng., Vol. 911, Amit Dhawan et al. (Eds): Advances in VLSI, Communication, and Signal Processing, Aishita Verma , Anum Khan , Subodh Wairya, 13 pages, Springer, Singapore , 2022, ,
  5. Low-Power High-Performance Hybrid Scalable, First International Conference on Computational Electronics for Wireless Communications. Lecture Notes in Networks and Systems, vol 329. Springer, Singapore. https://doi.org/10.1007/978-981-16-6246-1_14, Aishita Verma , A Khan , Subodh Wairya, 12 pages, Springer, Singapore. , 2022, ISBN : 978-981-16-6246-1,
  6. Performance Evaluation of Full Adder Using Magnetic Tunnel Junction, Proceedings of International Conference on Recent Trends in Computing. Lecture Notes in Networks and Systems, vol 341. Springer, Singapore. https://doi.org/10.1007/978-981-16-7118-0_44, Jyoti Garg , Subodh Wairya , 10 pages, Springer, Singapore , 2022, ISBN : 978-981-16-7118-0,
  7. Low-Power Shift Registers Using Fully Static Contention Free Single-Phase Clocked Flip Flop Recent Trends in Electronics and Communication. Lecture Notes in Electrical Engineering, vol 777. pp 495-510, Priti Tripathi , Anum Khan , Subodh Wairya, 16 pages, Springer, Singapore , 2022, ISBN : 978-981-16-2761-3,
  8. A Cost-Efficient QCA XOR Function Based Arithmetic Logic Unit for Nanotechnology Applications. International Conference on Innovative Computing and Communications. Advances in Intelligent Systems and Computing, Divya Tripathi , Subodh wairya , 16 pages, Springer, Singapore , 2022, ISBN : 978-981-16-2597-8,
  9. STT-MRAM A Universal Memory from Device to Circuit, (EMSME) Select Proceeding EMSME 2020, Lecture Notes in Electrical Engineering book series (LNEE, volume 766), Jyoti Garg , Subodh Wairya , 10 pages, Springer Nature Singapore Pte Ltd , 2022, ISBN : 978-981-16-1476-7,

2021

  1. Design and Performance Evaluation of Highly Efficient Adders in Nanometer Technology, Lecture Notes in Electrical Engineering, vol 683, Advances in VLSI, Communication, and Signal Processing, Prashasti, Jaiswal S , A Khan , S Wairya, 12 pages, Springer, Singapore , 2021, ISBN : 978-981-15-6840-4,
  2. Performance Evaluation of Energy-Efficient Adiabatic Logic Circuit-Based Multiplexer for Low Power Applications, Lecture Notes in Electrical Engineering book series (LNEE, volume 683), dvances in VLSI, Communication, and Signal Processing, S Jaiswal, Prashasti , A Khan , S Wairya, 11 pages, Springer, Singapore , 2021, ISBN : 978-981-15-6840-4,
  3. A Cost-Efficient Magnitude Comparator and Error Detection Circuits for Nano-Communication, Lecture Notes in Networks and Systems, vol 204, D, Tripathi , S. Wairya , 16 pages, Lecture Notes in Networks and Systems, vol 204. Springer, Singapore , 2021, ISBN : 978-981-16-1394-4,
  4. Performance Evaluation of Logic Gates Using Magnetic Tunnel Junction, Lecture Notes in Electrical Engineering, vol 749, Jyoti Garg , Subodh Wairya , 9 pages, Lecture Notes in Electrical Engineering, vol 749. Springer, Singapore , 2021, ISBN : 978-981-16-0289-4,

2020

  1. Full Adder with Self Checking Capability using Quantum Dot Cellular Automata, S. Kidwai , D. Tripathi , S. Wairya, 12 pages, Advances in VLSI, Communication, and Signal Processing Lecture Notes in Electrical Engineering book series, Springer , 2020, ISBN : 1876-1100,

2019

  1. Performance Evaluation of Energy-Efficient Adiabatic Logic Circuit-Based Multiplexer for Low Power Applications, Jaiswal S., , Prashasti, , Khan A., Wairya S., 683 pages, in VLSI, Communication, and Signal Processing. Lecture Notes in Electrical Engineering, vol. 683. Springer, Singapore , 2019, ,
  2. Design and Performance Evaluation of Highly Efficient Adders in Nanometer Technology, Prashasti , Jaiswal S., , Khan A., Wairya S., 683 pages, Advances in VLSI, Communication, and Signal Processing. Lecture Notes in Electrical Engineering, vol. 683. Springer, Singapore , 2019, ,

2015

  1. Optimized Approach for Reversible Code Converters Using Quantum Dot Cellular Automata, Neeraj Kumar Misra , Subodh Wairya , V. K. Singh, 11 pages, Advances in Intelligent Systems and Computing, Springer , 2015, ISBN : 978-81-322-2695-6,
Complete Book

2023

  1. Intelligent Systems and Smart Infrastructure Proceedings of ICISSI 2022, Brijesh Mishra , Rakesh Kumar Singh , Subodh Wairya, Manish Tiwari, 774 pages, CRC Press, Taylor & Francis Group, , 2023, ISBN : 9781032412870,

2017

  1. Design and Testability of Diverse Reversible Error Control Circuits, Neeraj Kumar Misra , Subodh Wairya , Bibhash Sen, 107 pages, LAP Lambert Academic Publishing German , 2017, ,

2006

  1. A Simplified Approach to Telecommunication and Electronic Switching Systems, C.B.L. Srivastav , Neelam Srivastava , Subodh Wairya, 318 pages, Dhanpat Rai and Company , 2006, ,
more
Displaying 1 - 161 of 161 publications

2025

  1. Anurag Yadav, Subodh Wairya, Charge Shared based Low Power and High-Speed Dynamic Comparator for High Frequency Analog Signal Processing Architecture, Integration The VLSI Journal, , vol. 103, pp. 102426, 2025. DOI : 10.1016/j.vlsi.2025.102426
  2. Anurag Yadav, Subodh Wairya, Design and Analysis of Low Power, High Speed and Sensing Small Differential Input Signal of Dynamic Comparator with Transconductance Improved Latching Stage, Journal of Circuits, Systems and Computers , Word Scientific, vol. 35, 2, pp. 2550365, 2025. DOI : 10.1142/S0218126625503657
  3. Sheetal Singh, Subodh Wairya, Effect of Hetero-Dielectric Gate on DC, RF/Analog, and Linearity Performance of Dual-Source Vertical TFET for Low-Power Applications, Semiconductors, , , , 2025.
  4. D. Sharma, A. Raj, A. Srivastava, A. Sharma, S. Wairya, Smart Traffic Flow Management System using FPGA," 2024 Second International Conference Computational and Characterization Techniques in Engineering & Sciences, Second International Conference Computational and Characterization Techniques in Engineering & Sciences, IEEE, , pp. 1-5, 2025. DOI : 10.1109/IC3TES62412.2024.10877430
  5. Archana, Subodh Wairya, D. Vaithiyanathan, M. Verm, Design and Optimization of Dual-Source Vertical TFETs: Comparing Overlapped and Non-Overlapped Channel Architectures, Devices for Integrated Circuit, IEEE , , pp. 89-94, 2025. DOI : 10.1109/DevIC63749.2025.11012303
  6. Sheetal Singh, Subodh Wairya, Effect of Hetero-Dielectric Gate on Direct Current, Radio Frequency/Analog, and Linearity Performance of Dual-Source Vertical Tunnel Field Effect Transistor for Low-Power Applications, Semiconductors, , vol. 59, pp. 650–660, 2025. DOI : https://doi.org/10.1134/S1063782625600664
  7. Sheetal Singh, Subodh Wairya, Heterojunction (SiGe/Si) triple metal dual gate extended source tunnel FET for improved DC, noise and linearity performance, Analog Integrated Circuits and Signal Processing, Springer US, vol. 125, 1, pp. 12, 2025. DOI : https://doi.org/10.1007/s10470-025-02492-z
  8. Rahul Singh, Subodh Wairya, Four Current Path PRFC OTA with Cross-Coupled Positive Feedback with improved gain and PSRR for Analog Signal Processing, Journal of Circuits, Systems, and Computers, World Scientific , , , 2025. DOI : https://doi.org/10.1142/S0218126626500994 WSPC-JCSC-D-25-01002
  9. Km. Akhya Pandey, Anurag Yadav, Subodh Wairya, Performance Analysis of High Speed Dynamic Comparator Topologies for Low Power VLSI Applications, International Conference on Electrical and Electronics Engineering , IEEE, , pp. 1-6, 2025. DOI : 10.1109/ICE367573.2025.11448824
  10. Km. Akhya Pandey, Anurag Yadav, Subodh Wairya, High Speed Double Tail Dynamic Comparator with Enhanced Amplification and Latch Stages Using Cascode and Charge Sharing Techniques, International Conference on Electrical and Electronics Engineering , IEEE, , pp. 1-6, 2025. DOI : 10.1109/ICE367573.2025.11448602

2024

  1. Anurag Yadav, Subodh Wairya, Design and Analysis of Low Power and High Speed Dynamic Comparator with Transconductance Enhanced in Latching stage for ADC Application, Journal of Circuits, Systems and Computers , Word Scientific, vol. 33, 11, pp. 2450198, 2024. DOI : 10.1142/S0218126624501986
  2. Anum Khan, Subodh Wairya, Efficient and Power-Aware Design of a Novel Sparse Kogge-Stone Adder using Hybrid Carry Prefix Generator Adder, Advances in Electrical and Computer Engineering, Stefan cel Mare University of Suceava, Romania, vol. Vol. 24, Issue 1, pp. 71-80, 2024. DOI : 10.4316/AECE.2024.01008
  3. Agyenya Anand, Anurag Yadav, Subodh Wairya, Performance Analysis of Fast & Power Efficient Dynamic Comparator Topologies, 2nd International Conference on Device Intelligence Computing and Communication Technologies, Graphic Era University, IEEE, , pp. 654-658, 2024. DOI : 10.1109/DICCT61038.2024.10533168
  4. Sheetal Singh, Subodh Wairya, Linearity and noise evaluation based analysis of extended source heterojunction double gate tunnel FET, Micro and Nanostructures, Elsevier, vol. 194, 207939, , 2024. DOI : https://doi.org/10.1016/j.micrna.2024.207939 Impact Factor : 3
  5. Sheetal Singh, Subodh Wairya, Performance Analysis for Electrical Noise Capabilities of TFET Configuration Topologies for Low Power Application, International Conference on Signal Processing and Advance Research in Computing , , , pp. 1-6, 2024. DOI : 10.1109/SPARC61891.2024.10828987

2023

  1. Jyoti Garg, Subodh Wairya, Design of Low Power Arithmetic logic unit using SHE assisted STT / MTJ, International journal of computing and digital systems, University of Bahrain, Bahrain, vol. 14, 1, pp. 107-115, 2023. DOI : http://dx.doi.org/10.12785/ijcds/140110
  2. Mohd Saqib, Subodh Wairya, Anurag Yadav, A 6.7GHz, 89.33 uW power and 81.26% tuning range dual input ring VCO with PMOS varactor, Journal of Circuits, Systems and Computers, World Scientific , World Scientific Publishing Company, , , 2023. DOI : 10.1142/S0218126623501992
  3. Aishita Verma, Anum Khan, Subodh Wairya, Design and Analysis of Efficient Vedic Multiplier for Fast Computing Applications, International Journal of Computing and Digital System, University of Bahrain, vol. 1, 13, pp. 190-201, 2023. DOI : http://dx.doi.org/10.12785/ijcds/050301
  4. Digvijay Pandey, Subodh Wairya, An optimization of target classification tracking and mathematical modelling for control of autopilot, The Imaging Science Journal, Taylor & Francis, vol. 70, 6, pp. 371-386, 2023. DOI : https://doi.org/10.1080/13682199.2023.2169987 Impact Factor : 1.072
  5. Sheetal Singh, Subodh Wairya, Sub-threshold Swing Analysis for NC-TFET in Low-Power Biomedical Applications, 2023 IEEE Devices for Integrated Circuit (DevIC), Kalyani, India,, 5th IEEE International Conference on Devices for Integrated Circuit, 2023, IEEE, , pp. 481-485, 2023. DOI : 10.1109/DevIC57758.2023.10134969
  6. Abhinav Saxena, Anurag Yadav, Subodh Wairya, Design Analysis of 3-Bit Flash ADC using Low-Offset and Low-Power Opamp, 10th International Conference on Signal Processing and Integrated Networks (SPIN 2023, IEEE Xplore Digital Library, , pp. 502-507, 2023. DOI : 10.1109/SPIN57001.2023.10116426
  7. Manoj Kumar Jain, Amrita Singh, Subodh Wairya, Configuration for a Grounded Lossy Impedance Simulator Employing CC-CFAs and Grounded Passive Elements, SERBIAN JOURNAL OF ELECTRICAL ENGINEERING, Faculty of Technical Sciences Cacak, vol. 20, Issue 2, pp. 147-162, 2023. DOI : https://doi.org/10.2298/SJEE2302147J
  8. Parikalp Gupta, Anum Khan, Subodh Wairya, Performance Analysis of Ternary Full Adder designs using proposed Ternary 3:1 MUX, 23-24 August, (TEECCON) REVA University, Bengaluru, India, Second International Conference on Trends in Electrical, Electronics & Computer Engineering, IEEE, , pp. 336-341, 2023. DOI : 10.1109/TEECCON59234.2023.10335872.
  9. Archana, Sheetal Singh, Subodh Wairya, Dual Source Vertical TFET Channel Overlapped Structure with Enhanced RF/Analog Performance for Low-Power- Applications, 23-24th August, (TEECCON) REVA University, Bengaluru, India, Second International Conference on Trends in Electrical, Electronics & Computer Engineering : Submission, IEEE , , pp. 198-203, 2023. DOI : 10.1109/TEECCON59234.2023.10335835
  10. Abhinav Saxena, Anurag Yadav, Subodh Wairya, Design Analysis of an Energy-Efficient Low-Power Dynamic Comparator Using NMOS Based Preamplifier, 6th-7th July 2023, (ICCCNT), IIT - Delhi, Delhi India, 14th International Conference on Computing, Communication and Networking Technology, IEEE, , , 2023. DOI : 10.1109/ICCCNT56998.2023.10307939
  11. Archana, Sheetal Singh, Subodh Wairya, Design and Analysis of Dual Source Vertical TFET with and without channel overlapped structure, 1-3rd July 2023 (Micro2023), Organizer: Applied Computer Technology, Kolkata, West Bengal, Venue: Hotel Vivanta, Guwahati, Assam, India, 10th International Conference on Microelectronics Circuits and Systems, Springer Singapore, , , 2023.
  12. Ayushi Kirti Singh, Subodh Wairya, Divya Tripathi, Cell Optimization and Realization of Vedic Multiplier Design in QCA, International journal of computing and digital systems, University of Bahrain, Bahrain, vol. 14, 1, pp. 10491-10503, 2023. DOI : http://dx.doi.org/10.12785/ijcds/1401116
  13. Anum Khan, Arindom Chakraborty, Upal Barua Joy, Subodh Wairya, Mehedi Hasan, Carry look-ahead and ripple carry method based 4-bit carry generator circuit for implementing wide-word length adder, Available online 8 September 2023, Page 105949, Microelectronics Journal, Elesvier, , pp. 105949, 2023. DOI : https://doi.org/10.1016/j.mejo.2023.105949
  14. Parikap Gupta, Anum Khan, Subodh Wairya, Performance Evaluation of Novel Ternary Subtractor Circuits using Double Pass Transistor Logic ” 4th Global Conference for Advancement in Technology (GCAT), BANGALORE, India. Oct. 06 - 08, 2023, "IEEE Conference, , , pp. 1-6, 2023. DOI : 10.1109/GCAT59970.2023.10353379

2022

  1. Anurag Yadav, Subodh Wairya, Performance and Area Optimization of SRAM Cell in Nanocomputing Application, Int. J. Com. Dig. Sys. 11, No.1 (Mar-2022), International Journal of Computing and Digital System, University of Bahrain, , pp. 1009-1026, 2022. DOI : https://dx.doi.org/10.12785/ijcds/120120
  2. Anum Khan, Subodh Wairya, Performance Evaluation of Highly Efficient XOR and XOR-XNOR Topologies using CNTFET for Nanocomputation, Int. J. Com. Dig. Sys. 12, No.1 (Jul-2022), International Journal of Computing and Digital System, University of Bahrain, , pp. 225-236, 2022. DOI : https://dx.doi.org/10.12785/ijcds/120120
  3. Digvijay Pandey, Subodh Wairya, A Novel Algorithm to Detect and Transmit Human-Directed Signboard Image Text to Vehicle Using 5G-Enabled Wireless Networks, International Journal of Distributed Artificial Intelligence , IGI Global publisher, , pp. 1-11, 2022. DOI : http://doi.org/10.4018/IJDAI.291084
  4. Divya Tripathi, Subodh Wairya, A Cost Efficient QCA Code Converters for Nano Communication Applications Int. J. Com. Dig. Sys. 12, No.1 (Jul-2022), International Journal of Computing and Digital System, University of Bahrain, , pp. 345-352, 2022. DOI : https://dx.doi.org/10.12785/ijcds/120128
  5. Binay Kumar Pandey, Digvijay Pandey, Subodh Wairya, Gaurav Agarwal, Pankaj Dadeech, Sanwta Ram Dogiwal, Sabyasachi Pramanik, Application of Integrated Steganography and Image Compressing Techniques for Confidential Information Transmission, Cyber Security and Network Security, John Wiley & Sons, Inc, , pp. 169-191, 2022. DOI : https://doi.org/10.1002/9781119812555.ch8
  6. Nashra Khalid, Anurag Yadav, Subodh Wairya, Performance analysis of various fast and low power dynamic comparators, Intelligent Systems and Smart Infrastructure – Brijesh Mishra et al. (eds) © 2023 Taylor & Francis Group, London, 1st International Conference on Intelligent Systems and Smart Infrastructure, jointly Organised by SIET, Prayagraj IET, Lucknow ,U.P. & Manipal University Jaipur, Rajasthan, on 21-22 May 2022., CRC Press Taylor &Francis, , pp. 64-72, 2022. DOI : 10.1201/9781003357346-9
  7. Kunal Kumar, Anurag Yadav, Subodh Wairya, Design and Analysis of High speed and Low Power Dynamic Comparator, Intelligent Systems and Smart Infrastructure – Brijesh Mishra et al. (eds) © 2023 Taylor & Francis Group, London, 1st International Conference on Intelligent Systems and Smart Infrastructure, jointly Organised by SIET, Prayagraj IET, Lucknow ,U.P. & Manipal University Jaipur, Rajasthan, on 21-22 May 2022., CRC Press, Taylor and Francis , , pp. 107-117, 2022. DOI : 10.1201/9781003357346-13
  8. Ayushi Kirti Singh, SubodhWairya, Divya Tripathi, A Comparative Performance Analysis of QCA Full Adder, 1st International Conference on Intelligent Systems and Smart Infrastructure, jointly Organized by SIET, Prayagraj IET, Lucknow ,U.P. & Manipal University Jaipur, Rajasthan, on 21-22 May 2022., CRC Press, Taylor and Francis , , , 2022.
  9. Vivek Mishra, Anurag Yadav, Subodh Wairya, Design of Compensated Supply Circuit Topology for a Ring Oscillator, International journal of computing and digital systems, University of Bahrain, , pp. 1005-1017, 2022. DOI : https://dx.doi.org/10.12785/ijcds/120181
  10. Nivedita Rai, Anurag Yadav , Subodh Wairya, Design of a High Speed and Low Power Charge Shared Based Dynamic Comparator for ADC Application, 1st International Conference on Advances in Computing and Future Communication Technologies, organized by Meerut Institute of Engineering and Technology, Meerut, India on 16-17 December, 2021, IEEE Explore, , pp. 125-130, 2022. DOI : doi: 10.1109/ICACFCT53978.2021.9837362.
  11. Digvijay Pandey, Subodh Wairya, Manvinder Sharma, Anuj Kumar Gupta, Rahul Kakkar, Binay Kumar Pandey, An approach for object tracking, categorization, and autopilot guidance for passive homing missiles, Aerospace Systems, Springer Nature Singapore, , pp. 1-14, 2022. DOI : https://doi.org/10.1007/s42401-022-00150-0
  12. Digvijay Pandey, Subodh Wairya, B Pradhan, Wangma, Understanding COVID-19 response by twitter users: A text analysis approach, Heliyon, Elsevier, , pp. 1-6, 2022. DOI : https://doi.org/10.1016/j.heliyon.2022.e09994
  13. Ayushi Kirti Singh, Subodh Wairya, Divya Tripathi, A Cell Optimization and Realization of XOR based Logic Design in QCA, International Conference on VLSI, Communication & Signal Processing , Springer , , pp. 39-69, 2022.
  14. Kunal Kumar, Subodh Wairya, Anurag Yadav, Design Analysis of Ultra Low Power Charge Sharing Based High Speed Comparator Topology, 3rd International Conference on VLSI, Communication & Signal Processing, Springer, , , 2022.
  15. Mohd Saqib, Subodh Wairya, Anurag Yadav, Performance Analysis of Differential Dual stage delay cells of VCO, 5th International Conference on VLSI, Communication & Signal Processing, Springer , , pp. 785-799, 2022. DOI : https://link.springer.com/chapter/10.1007/978-981-99-0973-5_60
  16. Jyoti Garg, Subodh Wairya, Performance Evaluation of Low Power Hybrid Combinational Circuits using Memristor, International Journal of Electrical and Electronics Research, FOREX, , pp. 998-993, 2022. DOI : 10.37391/IJEER

2021

  1. Divya Tripathi, Subodh Wairya, An Energy Dissipation and Cost Optimization of QCA Ripple Carry Adder, IEEE 8th International Conference on Signal Processing and Integrated Networks, SPIN-2021, organized by Amity University, Noida, IEEE , , pp. 760-765, 2021. DOI : 10.1109/SPIN52536.2021.9566068
  2. Jyoti Garg, Aishita Verma, Subodh Wairya, Memristor Emulator Circuits An Emerging Technology with Applications, International Conference On VLSI & Microwave and Wireless Technologies, NA, , , 2021.
  3. Aishita Verma, Anum Khan, Subodh Wairya, Low-Power high performance Hybrid Scalable Full Adder for Fast Computation, International Conference On Computational Electronics for Wireless Communication, NIT, Kurukshetra , NA, , , 2021.
  4. Anurag Yadav, Nivedita Rai, Subodh Wairya, Design of Flash ADC using low offset comparator for analog signal processing application, "IEEE 8th International Conference on Signal Processing and Integrated Networks, SPIN-2021, organized by Amity University, Noida , IEEE, , pp. 76-81, 2021. DOI : 10.1109/SPIN52536.2021.9566050
  5. Divya Tripathi, Subodh Wairya, An Energy Dissipation and Cell Optimization of Vedic Multiplier Topologies for Nanocomputing Applications, Turkish Journal of Computer and Mathematics Education , Science Research Society, , pp. 1490-1510, 2021. DOI : Vol.12 No.14 (2021), 1490– 1510. https://turcomat.org/index.php/turkbilmat/article/view/10473/7889
  6. Shilpi Gupta, Subodh Wairya, S Singh, Design and Analysis of Triple Metal Vertical TFET Gate Stacked with N-Type SiGe Delta-Doped Layer, Silicon, Springer Journals Publication, , pp. 4217-4225, 2021. DOI : https://doi.org/10.1007/s12633-021-01211-3
  7. Shilpi Gupta, Subodh Wairya, Performance analysis of different Tunnel Field Effect Transistors (TFET) device structures with their Challenges, IEEE 8th International Conference on Signal Processing and Integrated Networks, SPIN-2021, organized by Amity University, Noida, IEEE, , pp. 790-795, 2021. DOI : 10.1109/SPIN52536.2021.9566097
  8. Shilpi Gupta, Subodh Wairya, Shaliendra Singh, Analytical modeling and simulation of a triple metal vertical TFET with hetero-junction gate stack, Superlattices and Microstructures, Academic Press, , pp. 1-9, 2021. DOI : https://doi.org/10.1016/j.spmi.2021.106992, Volume 157, September 2021
  9. Semba Walli, SRP sinha, Subodh Wairya, Performance Improvement and Comparative Analysis of Memristive Emulator Networks, 2nd International Conference for Emerging Technology , IEEE, , pp. 6, 2021. DOI : 10.1109/INCET51464.2021.9456289
  10. Divya Tripathi, Subodh Wairya, An Efficient QCA Vedic Multiplier for Nanotechnology applications, The International Conference for Intelligent Technologies , IEEE Xplore Digital Library, , pp. 1-6, 2021. DOI : 10.1109/CONIT51480.2021.9498464
  11. Divya Tripathi, Subodh Wairya, A Cost efficient QCA RAM cell for Nanotechnology Applications, International Conference On VLSI & Microwave and Wireless Technologies MMMTU, Gorakhpur, India, NA, , , 2021.
  12. Anum Khan, Subodh Wairya, High Performance 3-2 Compressor using Efficient XOR-XNOR in Nanotechnology, International Conference On VLSI & Microwave and Wireless Technologies, MMMTU, Gorakhpur, India, NA, , , 2021.
  13. Digvijay Pandey, Subodh Wairya, Performance analysis of text extraction from complex degraded Image using fusion of DNN, steganography and AGSO, International Conference On VLSI & Microwave and Wireless Technologies, MMMTU, Gorakhpur, India, 20-21 March. 2021, NA, , , 2021.
  14. Semba Walli , Jyoti Garg, Subodh Wairya, Analog and Digital Applications of 4-T Based Memristor Emulator, International Conference On VLSI & Microwave and Wireless Technologies, MMMTU, Gorakhpur, India, 20-21 March. 2021., NA, , , 2021.
  15. Divya Tripathi, Subodh Wairya, A Cost-Efficient QCA XOR-XNOR Topology for Nanotechnology Applications, 2nd International Conference on Computing Communication, and Intelligent Systems , IEEE, , pp. 6, 2021. DOI : 10.1109/ICCCIS51004.2021.9397215
  16. Divya Tripathi, Subodh Wairya, A Cost-Efficient QCA XOR function based Arithmetic Logic Circuits for Nanotechnology Applications, 4th International Conference on Innovative Computing and Communication, Springer, Singapore, , pp. 16, 2021. DOI : Proceedings of ICICC 2021, Volume 2, https://doi.org/10.1007/978-981-16-1395-1_19
  17. Divya Tripathi, Subodh Wairya, A Cost-Efficient Magnitude Comparator and Error Detection Circuits for Nano Communication, 5th International Conference on Inventive Systems and Control, Springer, Singapore, , pp. 15, 2021. DOI : DOI https://doi.org/10.1007/978-981-16-1395-1_19
  18. Divya Tripathi, Subodh Wairya, A Cost Efficient QCA Compressor Topologies for Fast Nano Computing Applications, "IEEE 8th International Conference on Signal Processing and Integrated Networks, SPIN-2021, organized by Amity University, Noida , IEEE, , pp. 1024-1029, 2021. DOI : 10.1109/SPIN52536.2021.9565997
  19. B K Pandey, Digvijay Pandey, Subodh Wairya, Gaurav Agarwal, An Advanced Morphological Component Analysis, Steganography, and Deep Learning-Based System to Transmit Secure Textual Data, International Journal of Distributed Artificial Intelligence , IGI Global U.S.A, , pp. 40-62, 2021. DOI : 10.4018/IJDAI.2021070104
  20. Divya Tripathi, Subodh wairya, An Ultra Efficient QCA SRAM Cell for Nanotechnology Applications, 4th International Conference on VLSI, Communication & Signal Processing , Springer, Singapore, , , 2021.
  21. Aishita Verma, Anum Khan, Subodh Wairya, Performance Analysis of Vedic multiplier using High Performance XOR-MUX based adder for Fast Computation, 4th International Conference on VLSI, Communication & Signal Processing, Springer, Singapore, , , 2021.
  22. Shilpi Gupta, Subodh wairya, Performance Estimation of Different Tunnel Field Effect Transistor Based Biosensors used in the Biomedical and its Future Prospective, 4th International Conference on VLSI, Communication & Signal Processing, Springer, Singapore, , , 2021.
  23. Anum Khan, Subodh wairya, An Efficient ALU Architecture Topology for Nanotechnology Applications, IEEE 8th International Conference on Signal Processing and Integrated Networks, SPIN-2021, organized by Amity University, Noida, IEEE, , pp. 784-789, 2021. DOI : 10.1109/SPIN52536.2021.9566043
  24. B K Pandey, Digvijay Pandey, Subodh Wairya, Gaurav Agarwal, A Deep Neural Network-Based Approach for Extracting Textual Images from Deteriorate Images, EAI Endorsed Transactions on Industrial Networks and Intelligent Systems, EAI, , pp. e3, 2021. DOI : http://eprints.eudl.eu/id/eprint/7138/
  25. Digvijay Pandey, SubodhWairya, Raghda Salam Al Mahdawib, Saif Al-din M Najimc, Haitham Abbas Khalafd,Shokhan M Al-Barzinjic, Ahmed J Obaide, Secret data transmission using advance steganography and image compression, Int. J. Nonlinear Anal. Appl. Volume 12, Special Issue, Winter and Spring 2021, International Journal of Nonlinear Analysis and Applications, Semnan University, , pp. 1243-1257, 2021. DOI : 10.22075/ijnaa.2021.5635
  26. Binay Kumar Pandey, Digvijay Pandey, Subodh Wairya, Gaurav Aggarwal, Rahul Rastogi, Deep Learning and Particle Swarm Optimisation-Based Techniques for Visually Impaired Humans' Text Recognition and Identification, Augmented Human Research, Springer Singapore, , pp. 1-14, 2021. DOI : https://doi.org/10.1007/s41133-021-00051-5
  27. Akhil Gupta, Rohit Anand, Digvijay Pandey, N Sindhwani, Subodh Wairya, Binay Kumar Pandey, Prediction of Breast Cancer Using Extremely Randomized Clustering Forests (ERCF) Technique: Prediction of Breast Cancer, International Journal of Distributed Systems and Technologies, IGI Global Publisher, Hershey PA, USA, , pp. IJDST vol.12, no.4 2021: pp.1-15, 2021. DOI : http://doi.org/10.4018/IJDST.287859

2020

  1. Sana, Anum Khan, Subodh Wairya, Design and Analysis of Hybrid full adder Topology using Regular and Triplet Logic Design, International Journal of Innovative Technology and Exploring Engineering , Blue Eyes Intelligence Engineering & Sciences Publication, , , 2020. DOI : 10.35940/ijitee.L8024.1091220
  2. Pandey, D., Pandey, B.K., Wairya, S, Hybrid deep neural network with adaptive galactic swarm optimization for text extraction from scene images, Soft Comput, Springer Nature Singapore Pte Ltd, , pp. 1563-1580, 2020. DOI : https://doi.org/10.1007/s00500-020-05245-4
  3. Divya Tripathi, Subodh Wairya, Energy Efficient Code Converter For Nanotechnology Applications, Journal of Critical Reviews , NA, , , 2020. DOI : 10.31838 /jcr.07.13.448
  4. Digvijay Pandey, Binay Kumar Pandey, Dr. Subodh Wairya, Dr. Randy Joy M. Ventayen, Bilal Khan, Dr Monika Gupta, Dr. Tribhuwan Kumar., Analysis of Text Detection, Extraction and Recognition from Complex Degraded Images and Videos, Journal of Critical Reviews , NA, , , 2020.
  5. D. Pandey, Binay Kumar Pandey, Subodh Wairya, An Approach To Text Extraction From Complex Degraded Scene, International Journal of Computational and Biological Sciences, NA, , , 2020.
  6. Tripathi Divya, Subodh Wairya , An Energy Efficient Binary Magnitude Comparator for Nanotechnology Application, International Journal of Recent Technology and Engineering , Blue Eyes Intelligence Engineering & Sciences Publication, , , 2020. DOI : 35940/ijrte.F7000.038620
  7. Divya Tripathi, Sana, Subodh Wairya, Cell Optimization and Realization of MGDI QCA based Combinational Logic Circuits for Nanotechnology Applications, Published in IEEE Xplore Digital Library, NA, , , 2020.
  8. Jyoti Garg, Subodh Wairya, STT MRAM a Universal Memory from device to circuit, 1st International Conference on Energy, Materials Sciences & Mechanical Engineering, NA, , , 2020.
  9. Jyoti Garg , Subodh Wairya, Performance Evaluation of Logic Gates using Magnetic Tunnel Junction, Machine Learning Deep Learning and Computational Intelligence for Wireless Communication workshop-2020, NA, , , 2020.
  10. Divya Tripathi, Subodh Wairya, An Efficient Energy Ripple Carry Adder for Nanotechnology Applications, 3rd International Conference on VLSI, Communication & Signal Processing, NA, , , 2020.
  11. Priti Tripathi, Anum Khan, Subodh Wairya, Low Power Shift Registers using Fully Static Contention Free Single-Phase Clocked Flip-Flop, International Conference on VLSI, Communication & Signal Processing, NA, , pp. 1-14, 2020.
  12. Sweta Tripathi, Anum Khan , Subodh Wairya, Performance Evaluation of Charge Retention Feedback Pass Transistor Logic based Master Slave D Flip Flop in NanoTechnology, International Conference on VLSI, Communication & Signal Processing, NA, , pp. 1-14, 2020.
  13. Jyoti Garg, Niharika Varshney , Subodh Wairya, Comparative study of Magnetic Tunnel Junction based 4T-MRAM, International Journal of Advanced Research in Engineering and Technology, IAEME, vol. 11, 5, pp. 1178-1186, 2020. DOI : 10.34218/IJARET.11.5.2020.128

2019

  1. Prashasti, Jaiswal S., Khan A., Wairya S., Design and Performance Evaluation of Highly Efficient Adders in Nanometer Technology, 2nd International Conference on VLSI, Communication & Signal Processing, NA, , , 2019.
  2. Jaiswal S., Prashasti, Khan A., Wairya S. , Performance Evaluation of Energy-Efficient Adiabatic Logic Circuit-Based Multiplexer for Low Power Applications, 2nd International Conference on VLSI, Communication & Signal Processing , NA, , , 2019.
  3. Abhishek Shukla, Subodh Wairya, Design of Odd-Even Parity Generator using Six Transistors XOR-XNOR Module, International Research Journal of Engineering and Technology , NA, , , 2019.
  4. Digvijay Pandey, Binay Kumar Pandey, Subodh Wairya, Study of Various Types Noise and Text Extraction Algorithms for Degraded Complex Image, International Journal of Emerging Technologies and Innovative Research(JETIR), NA, , , 2019.
  5. Digvijay Pandey, Binay Kumar Pandey, Subodh Wairya, Study of Various Techniques Used for Video Retrieval, Journal of Emerging Technologies and Innovative Research, NA, , pp. 850-853, 2019.
  6. Prashasti, Shivangi Jaiswal, Anum Khan , Subodh Wairya, High Performance and Low Power D Flip-Flop using Pulsed Latch Technique, International Journal of Applied Engineering Research, NA, , pp. 301-305, 2019.
  7. Singh Amrita, Manoj Kumar Jain, Subodh Wairya, Novel Lossless Grounded and Floating Inductance Simulators Employing a Grounded Capacitor Based in CC-CFA, Journal of Circuits, Systems, and Computers, NA, , , 2019. DOI : 10.1142/S0218126619500932 Impact Factor : 0.595
  8. Prashasti, Jaiswal S., Khan A., Wairya S. , Design and Performance Evaluation of Highly Efficient Adders in Nanometer Technology, 2nd International Conference on VLSI, Communication & Signal Processing , NA, , , 2019.
  9. Jaiswal S., Prashasti, Khan A., Wairya S. , Performance Evaluation of Energy-Efficient Adiabatic Logic Circuit-Based Multiplexer for Low Power Applications, 2nd International Conference on VLSI, Communication & Signal Processing, NA, , , 2019.

2018

  1. S. Kidwai, Subodh Wairya, Study of QCA based digital logic circuits to be used in nanotechnology, Global Journal of Engineering Science and Researches, NA, , pp. 289-295, 2018.
  2. Divya Tripathi, Subodh Wairya, Performance evaluation of low power Carry save adder for VLSI applications, International Journal of VLSI design & Communication Systems, NA, , pp. 58, 2018. DOI : 10.5121/vlsic.2018.9305
  3. Raj Vikram Singh, Subodh Waira , Rajiv Kumar Singh , Harsh Vikram Singh, Robust Watermarking using Genetic Algorithm in DCT Domain, International Journal of Engineering and Technology, NA, , pp. 1202-1204, 2018. DOI : 10.14419/ijet.v7i3.12.17837
  4. Raj Vikram Singh, Subodh Wariya, Javed Ahmad, Balendu Bhushan Pandey, To conceal and secure digital data for intellectual property right in Medical Images using DCT and DWT in Watermarking Technique, 4th International Conference on “Challenges & Opportunities For Technological Innovation In India, NA, , , 2018.
  5. Ritesh Singh, Neeraj Kumar Misra, Subodh Wairya, Implementation of Non-restoring Reversible Divider Using a Quantum-Dot Cellular Automata, 4th International Conference on Computational Intelligence in Data Mining, Advances in Intelligent Systems and Computing, Springer, Singapor, , , 2018. DOI : 10.1007/978-981-10-8055-5_41
  6. Neeraj Kumar Misra, Bibhash Sen, Subodh Wairya, Bandan Boi, Novel parity preserving reversible Binary-to-BCD code converter with testability of building blocks in quantum circuit, Second International Conference on Computational Intelligence and Informatics, Advances in Intelligent Systems and Computing, Springer, Singapore, , , 2018. DOI : 10.1007/978-981-10-8228-3_35

2017

  1. Neeraj Kumar Misra, Subodh Wairya, Bibhash Sen, Design of conservative, reversible sequential logic for cost efficient emerging nano circuits with enhanced testability, Ain Shams Engineering Journal, Elsevier , , pp. 2027-2037, 2017. DOI : 10.1016/j.asej.2017.02.005 Impact Factor : 3.091
  2. Neeraj Kumar Misra, Bibhash Sen, Subodh Wairya, Towards designing efficient reversible binary code converters and a dual-rail checker for emerging nanocircuits, Journal of Computational Electronics, Springer, , pp. 442-458, 2017. DOI : 10.1007/s10825-017-0960-4 Impact Factor : 1.63
  3. Neeraj Kumar Misra, Bibhash Sen, Subodh Wairya, Bandan Boi, Testable Novel Parity-Preserving Reversible Gate and Low-Cost Quantum Decoder Design in 1D Molecular-QCA, Journal of Circuits, Systems, and Computers, World Scientific , NA, , pp. 1-26, 2017. DOI : 10.1142/S0218126617501456 Impact Factor : 0.595
  4. Neeraj Kumar Misra, Bibhash Sen, Subodh Wairya, Novel Tree Structure Based Conservative, Reversible BCD Adder With Added Testability In Quantum Circuits, Journal of Computational and Theoretical Nanoscience , NA, , pp. 2515-2527, 2017. DOI : 10.1166/jctn.2017.6772
  5. Neeraj Kumar Misra, Bibhash Sen, Subodh Wairya, Novel Conservative Reversible Error Control Circuits Based On Molecular-QCA, International Journal of Computer Applications in Technology, N, , pp. 1-17, 2017. DOI : ISSN: 1741-5047.Indexed in
  6. Neeraj Kumar Misra, Bibhash Sen, Subodh Wairya, Designing of an Energy-Efficient Nanoelectronics Architecture for Binary Comparator Based On Quantum-Dot Cellular Automata, SHRISTI : A Journal of Energy, Environment & Ecology at School of Management Science, Lucknow , NA, , , 2017.
  7. Raj Vikram Singh, Subodh Wairya, Review of Energy–Efficient Biometric Authentication System, International Conference on “Innovative Entrepreneurship and Startup, NA, , pp. 311-316, 2017.

2016

  1. Neeraj Kumar Misra, Bibhash Sen, Subodh Wairya, Designing Conservative Reversible N-Bit Binary Comparator for Emerging Quantum-Dot Cellular Automata Nano Circuits, Journal of Nanoengineering and Nanomanufacturing American Scientific Publisher, NA, , pp. 201-2016, 2016. DOI : 10.1166/jnan.2016.1286
  2. Prateek Agrawal, S.R.P. Sinha, Neeraj Kumar Misra, Subodh Wairya, Design of Quantum Dot Cellular Automata Based Parity Generator and Checker with Minimum Clocks and Latency, International Journal of Modern Education and Computer Science, NA, , pp. 11-20, 2016. DOI : 10.5815/ijmecs.2016.08.02
  3. Sonali Singh, Shraddha Pandey, Subodh Wairya, Modular Design of 2^n:1 Quantum Dot Automata Multiplexers and its Application via Clock zone based Crossover, International Journal of Modern Education and Computer Science, NA, , pp. 41-52, 2016. DOI : 10.5815/ijmecs.2016.07.05
  4. Shraddha Pandey, Sonali Singh, Subodh Wairya, Designing an Efficient Approach for JK and T flip-flop with Power Dissipation Analysis using QCA, International Journal of VLSI design & Communication Systems , NA, , pp. 29-48, 2016.
  5. Shashank Gupta, Subodh Wairya, Hybrid Code Converters using Modified GDI Technique, International Journal of Computer Applications, NA, , pp. 12-19 , 2016.
  6. Shashank Gupta, Subodh Wairya, A GDI Approach to Various Combinational Logic Circuits in CMOS Nano Technology, International Journal Of Engineering And Computer Science, NA, , pp. 16243-16247, 2016.
  7. Neeraj Kumar Misra, Subodh Wairya, V. K. Singh, Approach to Design a High Performance Fault-Tolerant Reversible ALU, International Journal of Circuits and Architecture Design, NA, , pp. 83-103, 2016. DOI : 10.1504/IJCAD.2016.075913
  8. Neeraj Kumar Misra, Bibhash Sen, Subodh Wairya, Designing Conservative Reversible N-Bit Binary Comparator For Emerging Quantum-Dot Cellular Automata Nano Circuits, Journal of Nano-engineering and Nonmanufacturing, American Scientific Publisher , NA, , pp. 1-16, 2016. DOI : 10.1166/jnan.2016.1286
  9. Prateek Agrawal, S.R.P.Sinha, Neeeraj Kumar Misra, Subodh Wairya, Design of Quantum Dot Cellular Automata Based Parity Generator and Checker with Minimum Clocks and Latency, International Journal of Modern Education and Computer Science, NA, , pp. 11-20, 2016. DOI : 10.5815/ijmecs.2016.08.02
  10. Prateek Agrawal, S.R.P. Sinha, Subodh Wairya, Quantum Dot Cellular Automata Based Parity Generator And Detector: A Review, International Journal of Electronics and Communication Engineering, NA, , pp. 41-50, 2016.
  11. Neeraj Kumar Misra, Subodh Wairya, V. K. Singh, Optimized Approach for Reversible Code Converters Using Quantum Dot Cellular Automata, 4th International Conference on Frontiers in Intelligent Computing: Theory and Applications , Advances in Intelligent Systems and Computing, Springer, , , 2016.
  12. Raj Vikram Singh, Subodh Wairya, Robust Information Hiding Technique for Image security In Open channel, International Conference of Advance Computational Techniques in Information and Communication Technology, NA, , , 2016.
  13. Shraddha Pandey, Sonali Singh, Subodh Wairya, QCA Implementation Of XOR Based Full Adder Circuit Using Clock-Zone Based Crossover, National Conference Emerging Trends in Electrical & Electronics Engineering, NA, , , 2016.
  14. Shashank Gupta, Subodh Wairya, A Technique for Enhancing Performance of the Arithmetic Circuit, National Conference Emerging Trends in Electrical & Electronics Engineering , NA, , , 2016.
  15. Neeraj Kumar Misra, Subodh Wairya, V. K. Singh, Optimized Approach for Reversible Code Converters Using Quantum Dot Cellular Automata, Advances in Intelligent Systems and Computing, Springer, , pp. 367-378, 2016. DOI : 10.1007/978-81-322-2695-6_31

2015

  1. Neeraj Kumar Misra, Subodh Wairya, Vinod Kumar Singh, Approaches to Design Feasible Error Control Scheme Based on Reversible Series Gates, European Journal of Scientific Research, NA, , pp. 224-240, 2015.
  2. Neeraj Kumar Misra, Subodh Wairya, Vinod Kumar Singh, Frame of Reversible BCD Adder and Carry Skip BCD Adder and Optimization Using New Reversible Logic Gates for Quantum-Dot Cellular Automata, Australian Journal of Basic and Applied Sciences, NA, , pp. 286-298, 2015.
  3. Vijata, Subodh Wairya, A Study of Two Stage Operational Transconductance Amplifier using Floating gate MOSFET, International Journal Of Engineering And Computer Science, NA, , pp. 14643-14648, 2015. DOI : 10.18535/ijecs/v4i10.17
  4. Neeraj Kumar Misra, Mukesh Kumar Kushwaha, Subodh Wairya, Amit Kumar, Cost Efficient Design of Reversible Adder Circuits for Low Power Applications, International Journal of Computer Applications , NA, , , 2015.
  5. Avinash Singh , Subodh Wairya, A 16-Bit Ripple Carry Adder Design Using High Speed Modified Feedthrough Logic, International Journal of Engineering And Computer Application, NA, , pp. 12058-12061, 2015.
  6. P Sharma,, Subodh Wairya, A Feasible Approach to Design a CMOS Domino Circuit at Low Power VLSI Application, International Journal Of Engineering And Computer Science, NA, , pp. 13055-13060, 2015.
  7. Avinash Singh, Subodh Wairya, An Improved Feedthrough Logic for Low Power and High Speed Arithmetic Circuits, International Journal of Science and Research, NA, , pp. 2277-2280, 2015.
  8. Ankita Agarwal, Subodh Wairya , Cross layer Optimization of Optical Node in High Speed Network, International Journal of Engineering Research & Technology , NA, , pp. 599-603, 2015.
  9. Neeraj Kumar Misra, Subodh Wairya, Vinod Kumar Singh, Evolution of structure of some binary group-based n-bit comparator, n-to-2n decoder by reversible technique, Journal of VLSI design & Communication Systems, NA, , pp. 9-22, 2015. DOI : 10.5121/vlsic.2014.5502

2014

  1. Neeraj Kumar Misra, Mukesh Kumar Kushwaha, Subodh Wairya, Amit Kumar, Feasible Methodology for optimization of a novel reversible binary compressor, International Journal of VLSI design & Communication Systems, NA, , pp. 1-22, 2014. DOI : 10.5121/vlsic.2015.6401
  2. Neeraj Kumar Misra, Subodh Wairya, Vinod Kumar Singh, Preternatural Low-Power Reversible Decoder Design in 90 nm Technology Node, International Journal of Scientific & Engineering Research, NA, , pp. 969-978 , 2014.
  3. Monika Jain, Subodh Wairya, Performance Evaluation of Low Power Dynamic Circuit Using Footed Diode Domino Logic, International Journal of Engineering and Computer Science , NA, , pp. 1-4, 2014.
  4. Neeraj Kumar Misra , Subodh Wairya , Vinod Kumar Singh, An Inventive Design of 4*4 Bit Reversible NS Gate, IEEE Xplore Digital Library, NA, , , 2014. DOI : 10.1109/ICRAIE.2014.6909323
  5. Ravi Prakash Verma, Subodh Wairya, Prateek Gargeya, Mohd. Irshad Khan, Designing Microstrip Band-pass Filter at 6 GHz, National Conference on Advances in Computer Communication and Embedded, NA, , , 2014.

2013

  1. Neeraj Kumar Mishra, Subodh Wairya, Low Power 32×32 bit Multiplier Architecture based on Vedic Mathematics Using Virtex 7 Low Power Device, International Journal Of Research Review In Engineering Science & Technology, NA, , pp. 34-37 , 2013.
  2. Deepa Rana , Subodh Wairya, Robust High Speed Full Adder Design For Low Power VLSI Design, 2nd International Conference on Emerging Trends in Engineering & Technology, NA, , , 2013.

2012

  1. Subodh Wairya, Rajendra Kumar Nagaria, Sudarshan Tiwari, Comparative Performance Analysis of XOR-XNOR Function based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design, International Journal of VLSI design & Communication Systems, AIRCC Publication, , pp. 221-242, 2012.
  2. Subodh Wairya, Rajendra Kumar Nagaria, Sudarshan Tiwari, Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design, VLSI Design, Hindawi Publication, , pp. 1-18, 2012. DOI : 10.1155/2012/173079

2011

  1. Subodh Wairya, Rajendra Kumar Nagaria, Sudarshan Tiwari, New Design Methodologies for High Speed Mixed-Mode CMOS Full Adder Circuits, International Journal of VLSI design & Communication Systems , AIRCC Publication, , pp. 78-98, 2011. DOI : 10.5121/vlsic.2011.2207
  2. Subodh Wairya, Rajendra Kumar Nagaria, Sudarshan Tiwari, New Design Methodologies for High-Speed Low-Voltage 1-Bit CMOS Full Adder Circuits, Journal of Computer Technology and Application, David Publications, , pp. 190-198, 2011.
  3. Subodh Wairya, Garima Singh, Vishant,, R. K. Nagaria and S. Tiwari, Design Analysis of XOR (4T) based Low Voltage CMOS Full Adder circuit, IEEE Xplore Digital Library, NA, , , 2011.
  4. Subodh Wairya, Pankaj Kumar Tripathi, Rajendra Kumar Nagaria, Sudarshan Tiwari, Novel Design Topologies for MOSCAP Majority Function Full Adder cells, Proc. International Conference on Frontiers of Computer Science, NA, , pp. 55, 2011.
  5. S. Wairya, V. Narendar, R. K. Nagaria, S. Tiwari, Design of High-Performance CMOS 1-Bit Full Adder Circuits for VLSI Application, Proc. International Conference on Advances in Electrical & Electronics Engineering, NA, , pp. 37-38, 2011.

2010

  1. R. K. Nagaria, Rakesh Kumar Singh, Subodh Wairya, On The New Design of Sinusoidal Voltage Controlled Oscillators Using Multiplier in CFA based Double Integrator Loop, Journal of Circuits, Systems and Computers , NA, , pp. 939-948, 2010. DOI : 10.1142/S0218126610006542 Impact Factor : 0.595
  2. S. Wairya, P. K. Tripathi, V. Narendar, R. K. Nagaria and S. Tiwari, A New High Performance Adder-Cell Design and Analysis with minimum Transistors, Proc. International Conference on Current Trends In Technology, NA, , pp. 1-6, 2010.
  3. S. Wairya, Himanshu Pandey, R. K. Nagaria, S. Tiwari, Ultra Low Voltage High Speed 1-Bit CMOS Adder, IEEE Proc. International Conference on Power, Control and Embedded Systems, NA, , pp. 1-6, 2010. DOI : 10.1109/ICPCES.2010.5700479
  4. S. Wairya, R. K. Nagaria, S. Tiwari, New Design Methodologies for High Speed Low-Power 1-Bit CMOS Full Adder Circuits, Proc. International Conference on Advances in Information, Communication Technology and VLSI Design, NA, , pp. 1-6, 2010.
  5. S. Wairya, R. K. Nagaria, S. Tiwari, A Novel CMOS Full Adder Topology for Low Voltage VLSI Applications, IEEE Proc. International Conference on Emerging Trends in Signal Processing & VLSI Design , NA, , pp. 1142-1146, 2010.
  6. S. Wairya, V. Narendar, R. K. Nagaria, S. Tiwari, Comparative Study of High–Speed Full adder Circuits for Low Voltage, IEEE Proc. International Conference on Recent Advances in e-Communication and i-Technology, NA, , pp. 90, 2010.

2009

  1. Sourabh Kamthey, T.N.Sharma, R. K. Nagaria , S. Wairya, A Novel Design for Testability of Multiple Precharged Domino CMOS Circuits, World Applied Sciences Journal , IDOSI Publication, , pp. 175-181, 2009.
  2. Adarsh Kumar Agrawal, S. Wairya, R.K. Nagaria, S. Tiwari, A New Mixed Gate Diffusion Input Full Adder Topology for High Speed Low Power Digital Circuits, World Applied Sciences Journal , IDOSI Publication, , pp. 138-144, 2009.
  3. Shiv Shankar Mishra, S. Wairya, R.K. Nagaria, S. Tiwari, New Design Methodologies for High Speed Low Power XOR-XNOR Circuits, Journal of World Academy of Science, Engineering and Technology , NA, , pp. 200-206, 2009.
  4. Rakesh Kumar Singh, Shardul Verma, S. Wairya, R. K. Nagaria , Realization of CFA Based Analog Wave Processors, National Conference titled “Cutting Edge Computer and Electronics Technology, NA, , pp. 537-541, 2009.

2008

  1. Neelam Srivastava , Subodh Wairya, Sanjay Singh, Nano-Materials revolutionized the world of Electronic Technology, National Conference on “Advanced Materials” Organized by Department of Chemistry, NA, , , 2008.

2007

  1. Neelam Srivastava, Subodh Wairya, Vision of Next Generation Networks: Architecture, Implementation and Services, National Conference Titled “Emerging Technologies and Trends in IT, NA, , pp. 253-263, 2007.
  2. Subodh Wairya, Neelam Srivastava, Usage Scenarios with Wi-Max for Mobile/High Speed Portable Broad band Data services Application, Zonal Seminar titled “Wireless for Broad Band & Multimedia Communication: A Global Perspective, NA, , pp. 63-71, 2007.

2005

  1. Subodh Wairya , Neelam Srivastava, An Overview of Dense Wavelength Division Multiplexing in Optical Networking, National Seminar on “Future Broadband, Wireless and Mobile Communication, NA, , , 2005.
  2. Subodh Wairya, Neelam Srivastava , Wi-Fi why needed and how implemented, organized by IIIT Allahabad, NA, , , 2005.

1998

  1. M. S. Singh , Subodh Wairya, Computer Application in Simulation Study of Electric Drives, Eighth Annual Conference of Vijnana Parishad of India with Special Theme on Computer Applications in Mathematics, Science and Engineering, NA, , , 1998.
Displaying 1 - 9 of 9

International

  1. AICTE Sponsored 2nd International conference on Advancement in Electronics & Communication Engineering (AECE-2022) - Raj Kumar Goel Institute of Technology (RKGIT) Ghaziabad, Uttar Pradesh, India Advisor
  2. International Conference on Intelligent Systems and Smart Infrastructure (ICISSI 2022) - Shambhunath Institute of Engineering and Technology, Prayagraj UP India, Institute of Engineering and Technology (IET) Lucknow, U.P India, and Manipal University Jaipur, Rajasthan India Chair
  3. Invited Lecture talk on “MEMS & Digital Design in VLSI Application” in five day online Faculty Development… - The FDP is sponsored by Online AICTE Training and Learning (ATAL) Academy Delhi and organized by Department of Electronics Engineering, IERT Prayagraj U.P. Invited Talk
  4. First International Conference on Advances in Computing and Future Communication Technologies (ICACFCT), 2021 - Meerut Institute of Engineering & Technology and ACIC MIET Co-Chair
  5. International Conference on VLSI, Communication & Signal Processing (VCAS-2021) - ECE Department MNNIT, Allahabad, India Chair
  6. Invited Lecture talk on “Advance Digital Circuit Design in VLSI Application” in five day online Faculty Development… - Department of Electronics & Communication Engineering, Atria Institute of Technology, Bangalore, held during 24th-28th August 2021 Invited Talk
  7. 8th International Conference on Signal Processing and Integrated Networks (SPIN-2021), Session Chair - Department of Electronics and Communication Engineering, Amity School of Engineering and Technology, Amity University Uttar Pradesh, Noida, India Chair

National

  1. Integration of Renewable Energy and Smart Grids for Smart Cities - Department of Electrical Engineering, Bansal Institute of Engineering and Technology, Lucknow, U.P. Advisor
  2. Data Analytics, Big Data, Machine Learning and Applications. - Department of Electrical Engineering, Bansal Institute of Engineering and Technology, Lucknow, U.P. Advisor
more

Doctor of Philosophy

  1. Performance Evaluation of Low Power High Speed VLSI Design and Application with Data Converter Architecture, Aunrag Yadav (PHD/19/ ECE/2461), 2025, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  2. Performance Investigation of Hetero-Dielectric and SiGe Heterojunction Gate Tunnel FET for Low Power Applications , Sheetal Singh (PHD/21/ECE/2715), 2025, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  3. Performance Evaluation of High Speed Digital Circuits In Nanotechnology Architecture, Anum Khan (PHD/17/ECE/2211), 2024, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  4. DWT and Neural Network based Watermarking for Medical Image Security, Raj Vikram Singh (PHD/15/ECE/190), 2024, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  5. Performance investigation of SiGe Heterojunction Gate stacked Triple metal Gate Vertical TFET for low power application, Shilpi Gupta (PHD/16/ECE/2175), 2023, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  6. Performance Analysis on Text Extraction from Complex Degraded Images, Digvijay Pandey (PHD/16/ECE/2172), 2023, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  7. Performance Evaluation of Non Volatile Memory for low power VLSI application, Jyoti Garg (PhD/15/ECE/2055), 2023, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  8. Performance Evaluation of Low Power, High Speed Arithmetic Logic Circuits in Nanotechnology, Divya Tripathi (PHD/13/ECE/1413), 2022, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  9. Design and Testability of Diverse Reversible Logic Circuits for Low cost Nanoelectronics Application, Neeraj Kumar Mishra (PhD/13/ECE/1134), 2017, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow

Master of Technology

  1. Performance Analysis of Low Voltage, Low Power Bulk Driven OTA for VLSI Applications, Priya Singh, 2025, I.E.T Lucknow
  2. Performance Analysis of Dynamic Comparator Topologies for VLSI Applications, Akhya Pandey, 2025, I.E.T Lucknow
  3. ENERGY EFFICIENT ARCHITECTURES OF DYNAMIC COMPARATOR FOR LOW POWER VLSI APPLICATION, Abhinav Saxena, 2023, IET Lucknow
  4. PERFORMANCE AND DESIGN ANALYSIS OF TERNARY ARITHMETIC LOGIC CIRCUITS, Parikalp Gupta, 2023, IET Lucknow
  5. Design and Analysis of Dual Source Vertical TFET with and without channel overlapped structure For Low Power Applications, Archana, 2023, IET Lucknow
  6. Performance Evaluation and Analysis of Differential Dual stage delay cells VCO, Mohd Saqib, 2022, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  7. Low Power Dynamic Comparator Topologies for VLSI, Kunal Kumar, 2022, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  8. Design and Realization of QCA based Logic Designs, Ayushi Kirti Singh, 2022, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  9. Performance Evaluation and Analysis of Comparator Design in VLSI Application, Nivedita Rai, 2021, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  10. Performance Analysis of Hybrid Full Adder and Multiplier Topologies for Fast Computation, Aishita Verma, 2021, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  11. Power Efficient Frequency Divider Circuit for VLSI Applications, Vivek Saxena, 2020, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  12. MOSFET Based Memristor Emulator Circuit Analysis and Applications, Semba Walli, 2020, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  13. Implementation of Process Supply Voltage and Temperature Compensated Supply Circuit for A Ring Oscillator, Vivek Mishra, 2020, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  14. Low Power Voltage Controlled Oscillator (VCO) Using Multi-Threshold Transistors and Power gating Technique in Deep Submicron Technology, Sweta Tripathi, 2020, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  15. Low Power Shift Registers Using Contention Free Single-Phase Clocked Flip Flop, Priti Tripathi, 2020, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  16. Implementation of MGDI and Transmission Gate Based Hybrid CMOS Full Adders Using Triplet Design Approach, Sana, 2020, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  17. Performance Evaluation of Combinational circuit based on Energy Efficient Adiabatic Logic Technology for Ultra Low-Power Applications, Shivangi Jaiswal, 2019, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  18. Performance Evaluation of High Speed and Low Power Digital Circuits using Energy Efficient XOR & XNOR logic gates, Prashasti, 2019, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  19. Designing and Performance Comparison of Parity Generators Using Various XOR-XNOR modules, Abhishek Shukla, 2019, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  20. Design of Full Adder with self checking capability using QCA, Shahneela Jamal Kidwai, 2018, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  21. Performance Evaluation and design implementation of SRAM Semiconductor Memory in Nanotechnology, Anshu Arya, 2018, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  22. Contact thickness effect on mobility of Organic Thin Film Transistor and tradeoff with current on-off ratio, Bhoopendra Vikram Singh, 2018, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  23. “Design Analysis for SRAM in Nano-Technology”, Yogesh Singh, 2018, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  24. Efficient design of even and odd parity generator using different XOR-XNOR modules in VLSI design circuit, Sakshi Gupta, 2017, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  25. “Implementation of non-restoring reversible divider using QCA”, Ritesh Singh, 2017, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  26. Design analysis of low pass GDI circuit in sub-threshold region, Ragni Tripathi, 2017, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  27. Modular Design Of 2n*1 QCA Multiplexers and its application Via Clock Zone based Crossover, Sonali Singh, 2016, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  28. Designing An Efficient JK and T Flip Flop using QCA with Power Dissipation Analysis, Shraddha Pandey, 2016, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  29. Design Of Hybrid Code Converters Using Modified Gate Diffusion Input Technique, Shashank Gupta, 2016, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  30. Temperature Dependent Leakage Power Characteristic of Dynamic Circuit in Nanometer CMOS Technologies, Shivani Shukla, 2015, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  31. Design and Analysis of Different Topologies of CMOS Operational Trans-conductance Amplifier, Vijata, 2015, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  32. Design and Performance Analysis of Dynamic Circuits using Multi-Threshold Technique for Low Power VLSI Circuits, Anjali Tiwari, 2015, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  33. Cross layer optimization of Optical node in High Speed Network, Ankita Agarawal, 2015, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  34. Filter Antenna Module using Substrate Integrated Waveguide, Ravi Prakash Verma, 2015, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  35. Performance Analysis of GDI Based 1-Bit Full Adder Circuit for Low Power & High Speed Application, Shweta Kumari, 2015, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  36. Implementation and Analysis of Adiabatic Logic Circuits, Archita Srivastava, 2015, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  37. Realization and study of Low Power CMOS Current Feedback Amplifier, Nidhi Gupta, 2014, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  38. Study and Design of Low Power and Leakage Proof Digital Circuits, Monika Jain, 2014, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  39. Design and Analysis of Ultra Low Power SRAM Cache Memory Cell, Rahul Verma, 2014, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  40. Performance Analysis of High Speed Adiabatic Digital Logic Circuits, Sapna Dixit, 2013, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  41. Low Power Design Analysis of Array Multipliers Using Hybrid CMOS Full Adder Circuits, Ritika Mishra, 2012, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  42. Design Analysis of Mixed Chain Full Adder Circuits for VLSI Applications, Meenakshi Shree, 2012, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  43. Design Analysis of High-Speed XOR/XNOR based Logic Circuits Suitable for Low Power VLSI Applications, Divya Tripathi, 2012, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow
  44. Performance Analysis of High Speed Low Voltage CMOS Full Adder Circuits, Garima Singh, 2012, Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow