Impact of interface trap charges on device level performances of a lateral vertical gate stacked Ge Si TFET on SELBOX substrate | Institute of Engineering & Technology, Lucknow

Link

Year of Publication

2020

Other Authors

Prince Kumar Singh, and Satyabrata Jit

Type

Journals

Published in

Publication Title

Impact of interface trap charges on device level performances of a lateral/vertical gate stacked Ge/Si TFET-on-SELBOX-substrate

Status

International

First Author

Ashish Kumar Singh

Second Author

Manas Ranjan Tripathy

Third Author

Kamalaksha Baral,

Impact Factor

1.810

Status of Paper

Published

Nature

SCI

Publisher

Refereed/Peer Reviewed

Month of Publication

Aug

Council/Bodies

Institute of Engineering & Technology,
Sitapur Road,Lucknow
Uttar Pradesh
India
Pin Code : 226021