Assistant Professor (Contract)
Electronics & Communication Engineering Department
Self Finance Department
[email protected]
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Book Chapter

2023

  1. Intelligent Systems and Smart Infrastructure, Nashra Khalid , Anurag Yadav , Anurag Yadav, 8 pages, Apple Academic Press Inc. by CRC Press, a Taylor & Francis Group , 2023, ISBN : 978-1-032-41287-0,
  2. Intelligent Systems and Smart Infrastructure, Kunal Kumar , Anurag Yadav , Subodh Wairya, 11 pages, Apple Academic Press Inc. by CRC Press, a Taylor & Francis Group , 2023, ISBN : 978-1-032-41287-0,
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Displaying 1 - 14 of 14 publications

2023

  1. Saqib, Mohd, Subodh Wairya, Anurag Yadav, A 6.7 GHz, 89.33 μW power and 81.26% tuning range dual input ring VCO with PMOS varactor, Journal of Circuits, Systems and Computers , World Scientific, , , 2023. DOI : https://doi.org/10.1142/S0218126623501992
  2. Abhinav Saxena, Anurag Yadav, Subodh Wairya, Design Analysis of 3-Bit Flash ADC using Low-Offset and Low-Power Opamp, IEEE Xplore Digital Library, 10th International Conference on Signal Processing and Integrated Networks, , pp. 502-507, 2023.
  3. Abhinav Saxena, Anurag Yadav, Subodh Wairya, Design Analysis of an Energy-Efficient Low-Power Dynamic Comparator Using NMOS based Preamplifier, THE 14th INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATION AND NETWORKING TECHNOLOGIES , IEEE Xplore Digital Library, , pp. 1-6, 2023. DOI : 10.1109/ICCCNT56998.2023.10307939

2022

  1. Anurag Yadav, Subodh Wairya, Performance and Area Optimization of SRAM Cell in Nanocomputing Application, International Journal of Computing and Digital System, University of Bahrain, , pp. 1009-1026, 2022. DOI : https://dx.doi.org/10.12785/ijcds/110182
  2. Vivek Mishra, Anurag Yadav, Subodh Wairya, Design of Compensated Supply Circuit Topology for a Ring Oscillator, International Journal of Computing and Digital System, University of Bahrain, vol. 12, 1, pp. 1005-1017, 2022. DOI : https://dx.doi.org/10.12785/ijcds/120181
  3. Saqib, Mohd, Anurag Yadav, Subodh Wairya, Performance Analysis of Differential Dual Stage Delay Cells of VCO, International Conference on VLSI, Communication and Signal processing, Singapore: Springer Nature Singapore, , pp. 785-799, 2022.
  4. Kunal, Anurag Yadav, Subodh Wairya, Design of Ultralow-Power and High-Speed Comparator Using Charge Sharing Technique, 4th International Conference on VLSI, Communication and Signal Processing , Singapore: Springer Nature Singapore, , pp. 81-96, 2022.

2021

  1. A. Yadav, N. Rai, A. Verma , S. Wairya, Design of Flash ADC using low offset comparator for analog signal processing application, "IEEE 8th International Conference on Signal Processing and Integrated Networks, SPIN-2021, organized by Amity University, Noida , IEEE Xplore Digital Library, , , 2021.
  2. Nivedita Rai, Anurag Yadav, Subodh Wairya, Design of a High Speed and Low Power Charge Shared Based Dynamic Comparator for ADC Application, 1st International Conference on Advances in Computing and Future Communication Technologies, organized by Meerut Institute of Engineering and Technology, Meerut, India on 16-17 December, 2021, IEEE Xplore Digital Library, , , 2021.
  3. A. Yadav, N. Rai, A. Verma , S. Wairya, Design of Flash ADC using low offset comparator for analog signal processing application, 8th International Conference on Signal Processing and Integrated Networks, IEEE Xplore Digital Library, , pp. 76-81, 2021.

2016

  1. Anurag Yadav, Rajesh Mehra, Deep Sehgal , H.S. Jatana, High Performance Column Level ADC for CMOS Imager using Switched Capacitor Technique, International Journal of Advanced Research in Computer and Communication Engineering, International Journal of Advanced Research in Computer and Communication Engineering, vol. 5, 7, pp. 451-456, 2016. Impact Factor : 5.332
  2. Anurag Yadav, Rajesh Mehra, Deep Sehgal , Optimized Design of Column Level ADC for CMOS Imager using 180 nm Technology, IOSR Journal of VLSI and Signal Processing , IOSR Journal of VLSI and Signal Processing, vol. 6, 4, pp. 20-25, 2016. Impact Factor : 2.82

2015

  1. Anurag Yadav, Area Efficient 4-Bit Full Adder Design using CMOS 90 nm Technology, 1st International conference on Electronic Design Innovations & Technologies , Int. Journal of Electrical & Electronics Engg, vol. 2, 1, pp. 45-48, 2015.

2014

  1. Anurag Yadav, Rajesh Mehra, FPGA based IIR Filter Design Analysis for Different Orders, 6th international conference on Innovative trends in mechanical, Manufacturing, Automobile, Aeronautical Engineering and Applied Physics , Journal of Basic and Applied Engineering Research, vol. 1, 12, pp. 106-109, 2014.