Content Owner / Guide
Title
Performance Analysis of Dynamic Comparator Topologies for VLSI Applications
Year Awarded (Blank if Not Awarded)
2025
Awarding Body
Type
Master of Technology
Place of Work
E-Mail
Co Guide (Non IET)
Anurag Yadav
Roll No
2300521195003
Registration Date
Area of Research
Analog Signal Processing for Nano VLSI Design

