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Institute of Engineering & Technology, Lucknow
अभियांत्रिकी एवं प्रौद्योगिकी संस्थान, लखनऊ
An Autonomous Constituent Institute of Dr. A.P.J. Abdul Kalam Technical University Uttar Pradesh, Lucknow


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IEEE



Performance investigation of p Channel Hetero Junction GaN Tunnel FET

  • Read more about Performance investigation of p Channel Hetero Junction GaN Tunnel FET

Study and Investigation of DC and RF Performance of TFET on SEL BOX and Conventional SOI TFET with SiO2 HfO2 Stacked Gate Structure

  • Read more about Study and Investigation of DC and RF Performance of TFET on SEL BOX and Conventional SOI TFET with SiO2 HfO2 Stacked Gate Structure

Dual Material Stacked Hetero Dielectric Junctionless Accumulation Mode Nanotube MOSFET for enhanced Hot Carrier and Trapped Charges Reliability

  • Read more about Dual Material Stacked Hetero Dielectric Junctionless Accumulation Mode Nanotube MOSFET for enhanced Hot Carrier and Trapped Charges Reliability

Performance evaluation of double gate III V heterojunction tunnel FETs with SiO2 HfO2 Gate oxide structure

  • Read more about Performance evaluation of double gate III V heterojunction tunnel FETs with SiO2 HfO2 Gate oxide structure

Performance Analysis of Nanotube Junctionless Accumulation Mode MOSFETs with Ion Implanted Doping Profile

  • Read more about Performance Analysis of Nanotube Junctionless Accumulation Mode MOSFETs with Ion Implanted Doping Profile

Dual Material Ferroelectric Stacked Gate SiO2 PZT SOI Tunnel FETs with Improved Performance Design and Analysis

  • Read more about Dual Material Ferroelectric Stacked Gate SiO2 PZT SOI Tunnel FETs with Improved Performance Design and Analysis

Performance evalution of heterojunction SOI Tunnel FET with temperture

  • Read more about Performance evalution of heterojunction SOI Tunnel FET with temperture

A Simulation Based Study for Electrical Characteristics of SOI TFETs With Ferroelectric Stacked Gate Oxide Structure

  • Read more about A Simulation Based Study for Electrical Characteristics of SOI TFETs With Ferroelectric Stacked Gate Oxide Structure

Performance Analysis and Optimization of Nanotube Junctionless Accumulation MOSFETs with Lateral HfO2 SiO2 Gate oxide Structure

  • Read more about Performance Analysis and Optimization of Nanotube Junctionless Accumulation MOSFETs with Lateral HfO2 SiO2 Gate oxide Structure

Subthreshold Swing Modeling of Gaussian Doped Double Gate MOSFETs and its Validation Based on TCAD Simulation

  • Read more about Subthreshold Swing Modeling of Gaussian Doped Double Gate MOSFETs and its Validation Based on TCAD Simulation

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Council/Bodies


  • E-Cell
  • IEEE Students Chapter UNIT STB62961
  • Institution's Innovation Council
  • ISSACC
  • Navyug Navachar Foundation

Co-curriculars


  • Shauryotsava
  • Electrical Engineering Society
  • Encore
  • Google Developer Student Club
  • ISSACC
  • Mechanical Engineering Forum (MEF)
  • PARMARTH
  • Society for Electronics Exploration and Development (SEED)

IET in News


  • आईईटी को मिला स्वदेशी परम शावक डीएल कंप्यूटर : Amar Ujala
  • IET student's startup idea wins 1.5L award : Times of India
  • Deep learning, AI to help patients with brain injuries : Times of India
  • IET sets up centers for green hydrogen & electric vehicles : Times of India
  • 'सात फेरे' स्टार्टअप से शादी की सब बुकिग एक ही जगह : Hindustan Times

Contact Us


Institute of Engineering & Technology,
Sitapur Road,Lucknow
Uttar Pradesh
India
Pin Code          :   226021
 

Web: https://www.ietlucknow.ac.in



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