Design of Power Efficient Low-Offset Dynamic Latch Comparator using 90nm CMOS Process Read more about Design of Power Efficient Low-Offset Dynamic Latch Comparator using 90nm CMOS Process
A 0.55V, 28.6ppm/oC Nanopower Subthreshold Voltage Reference with Body Biasing Read more about A 0.55V, 28.6ppm/oC Nanopower Subthreshold Voltage Reference with Body Biasing
Design and Performance of High-speed Low-Offset CMOS Double-Tail Dynamic Comparators using Offset Control Scheme Read more about Design and Performance of High-speed Low-Offset CMOS Double-Tail Dynamic Comparators using Offset Control Scheme
A High-Speed Energy-Efficient CMOS Dynamic Latch Comparator for Low-Voltage Applications Read more about A High-Speed Energy-Efficient CMOS Dynamic Latch Comparator for Low-Voltage Applications
Impact of Channel Doping Fluctuation and Metal Gate Work Function Variation in FD-SOI MOSFET for 5nm BOX Thickness Read more about Impact of Channel Doping Fluctuation and Metal Gate Work Function Variation in FD-SOI MOSFET for 5nm BOX Thickness
Electronically Tunable First Order Universal Filter based on CCDDCCTA Read more about Electronically Tunable First Order Universal Filter based on CCDDCCTA
A variation and noise tolerant wide fan-in OR-Logic Domino circuit Read more about A variation and noise tolerant wide fan-in OR-Logic Domino circuit
LVLP high gm bulk-driven folded cascode OTA using current shunt auxiliary pair Read more about LVLP high gm bulk-driven folded cascode OTA using current shunt auxiliary pair
Linearity Enhancement using Bulk-Degeneration for Source Degenerated OTAs Read more about Linearity Enhancement using Bulk-Degeneration for Source Degenerated OTAs
Highly Linear Source Degenerated OTA Using Floating Gate MOSFET Technique Read more about Highly Linear Source Degenerated OTA Using Floating Gate MOSFET Technique
