Shilpi Gupta (PHD/16/ECE/2175)

Abstract The work carried out in this thesis is concerned with the design of electronic logic circuits. The invention of the transistor transformed the electronic industry, and microelectronics continues to have a significant impact on all aspects of development. The spectacular success story of microelectronics, on the other hand, cannot continue indefinitely due to three critical constraints in microelectronics, which include: • Fundamental Physical Limitations; • Material Limitations; • Technology Limitations; • Device Limitations and • Circuit and System Limitations. As MOSFET devices are scaled down to nanometer range (Nano-electronics), transient quantum effects impair their behavior. Alternative fault tolerant technologies are exploited. In the Complementary Metal-Oxide - Semiconductor (CMOS) technology, over the past four decades, scaling has been a gateway to continuous development in the silicone-based semiconductor industry. However, as the nanometer-sized technology development framework for the goal of building ultra-high-density integrated electronic computers and expanding performance, CMOS devices face fundamental problems such as increased leakage currents, large variations in process parameters, short channel effects, higher production costs, etc. The new technology will need to be energy-efficient, dense, and allow more tool features, per unit area and time. There are many nanoscale novels; this thesis discusses and summarizes advances in semiconductor device production of Low Power vertical design Tunnel Field-Effect Transistors (TFETs). Owing to its steeper sub-threshold (SS), tunnel FETs are helpful tools for ultra-low power applications having very low OFF current. Their operations are based on the controlled switching of quantum-mechanical Band-to-Band Tunneling (BTBT), instead of the thermionic emissions. This work deals with the novel characterization of n+ SiGe δ-doped layer with the combination of gate stacking method in Vertical TFET device by using TCAD simulation tool. The vertical structure will enhance the device’s scalability because of vertical electron tunneling for vertical electrical field. Therefore, higher ON state current offers due to parallel movement of charge carriers to the gate electric field. The introduction to the optimized n+ Si0.2Ge0.8 δ-doped layer will further reduce the off-state leakage current and enhance device performance because it minimizes the tunneling bandwidth between the source and channel junction. Triple metal gate is introduced to mitigate the unwanted ambipolar conduction and optimized the work function at tunneling gate, control gate and auxiliary gate with the value of 4.15eV, 4.3eV and 4.15eV. Four of the different combination have been discussed and compared with and without presence of the gate stack and n+ δ-doped layer. The reported data revels that among all different structures, the existence of gate staking method and SiGe δ-doped layer will show the 40 % improvement with existing simulations. A high current ratio of the order (~1013), with substantially benchmarking results of steeper subthreshold slope (9.75 mV/decade) is achieved. The simulation results conclude the n+ δ-doped TMG vertical TFET as a sustainable candidate for ultralow power applications. To verify the simulation part, we deals with approximate 2D analytical model for surface potential of a gate stacked triple metal Vertical TFET with n+ delta doped layer (δ-doped n+ SiGe GS-TMG-VTFET). The parabolic approximation process is used to solve the Poisson equation in terms of channel surface potential and electrical field respectively. The proposed method consists of a dual modulation effect that controls the surface potential at both the interface of the source and drains with the channel. This structure comprises SiO2 and HfO2 as gate-stacked materials to extend the control of the gate terminal over the channel. In addition, the proposed TMG-VTFET outperforms the surface potential results in terms of input and output characteristics like gate-source voltage (VGS) and drain-source voltage (VDS), gate oxide, and SiGe mole fraction. Finally, we obtained the expression of the channel surface potential, which involves the biasing variation of source and drain terminal. Our proposed model is accounting the variable of kane model in respect to extract the drain current characteristics. It can be modeled by integrating band-to-band tunneling generation rate using suitable boundary conditions. Now, efficiency of the proposed model for both the surface potential and drain current has been confirmed by comparing its analytical outcomes with the TCAD results. Finally, to extend with the application part this device is used as a TFET-based-biosensor. With the help of Silvaco TCAD reproductions, it is easy to obtained the new discovery that TFET sensors are more modest sub-threshold swing and limit voltage in respect to those of conventional(c)-FET sensors. This Vertical distribution of source, channel and drain will enhance the stability of the device. The integrated effect of the vertical tunneling as compare to lateral tunneling will enhance the device sensitivity and decrease the subthreshold slope. The Gate stacking of High-K (HfO2) with (SiO2) and the two-side gate metal electrode makes a good electrostatic control over a proposed device. Also, with the presence of SiGe layer in between source-channel interface will leads to the decrease in the tunneling barrier and enhance the device performance by reducing the energy band gap from 1.1eV to 0.7eV. Likewise, TFET based different sensors are further developed affectability because of their more extreme sub-threshold slant. Besides, TFET based-sensors is capable to detect 2-distinct atoms through inverse responsibilities in a single gadget. By utilizing two kinds of burrowing, for example, source-to-channel a lot to-deplete burrowing, the discovery of two distinctive objective particles is directed effectively at a similar detecting current-levels causes of the bipolar conduct of TFETs. In a typical source-speakers circuit, it is the affirmation with two distinctive objective particles could be likewise detected with the help of identical affectability. In light of these outcomes, we suppose that TFET based-Bio-sensors possibly will depiction another Vision in bio-detecting utilizations. Utilizing work function values appropriate for the above metals, p+ regions are generated close to the source field. By using Silvaco ATLAS TCAD simulator, the proposed structure's characteristics are investigated using the surface potential, electric field and energy bandgap diagrams for bio sensors. • Some of the special contributions include in this thesis are as follows: As TFETs are highly employable in various Low power circuits, the different technologies to implement these devices to offer large scale improvements in parameters like SS value, on current, off current, on to off current value ratio. By reviewing thoroughly, the most suited structures of n+ delta-doped SiGe layer Gate Stacked Triple Metal Gate Vertical TFET is proposed and simulate. Using these designs, the following objectives are proposed to be addressed in the circuits.  The examination of several TFET topologies shows that although on-current and ambipolarity are degraded, steeper subthreshold enable TFET to operate for very low power signals. When paired with a double gate TFET (DGTFET), which doubles the on-current, a single gate SOI TFET may achieve a subthreshold swing of 52.8 mV/decade. Later, Germanium (Ge) was utilized as a source material in place of Silicon due to Ge's low bandgap material and improved performance and large ON/OFF current ratio. Plasma TFET, which has a source and drain that are strongly doped and produce an incredibly small SS, reduces the ambipolarity of the device more than bilayer TFET, which is utilized to improve it.  To achieve a higher Ion to Ioff ratio, better SS value, and to lessen the SC i.e. short channel impact than MOSFET devices, certain conditions are being chosen in this work to use a different structure of Vertical Tunnel Field Effect Transistor (TFET) technology using semiconductor material. The device's scalability will be increased by vertically rearranging the source channel and drain. At the interface of source and channel, The SiGe layer is employed to minimize the energy band gap, or transmission barriers, from 1.1 eV to 0.7 eV, thereby expanding the band to band tunnelling medium.  The suggested device's performance is being evolved like an efficient aspirant for operating with all parameters in the subthreshold regime, making it appropriate for low power applications. As a result, it can be applied to new low power, sub-threshold application devices. We used SILVACO TCAD simulation software to develop and simulate an n+ delta-doped SiGe layer Gate Stacked Triple Metal Gate Vertical TFET in order to fill up research gaps.  In addition, the suggested device has been further refined utilising four distinct configurations: (a) TMG VTFET (b) GS TMG VTFET (c) Delta doped N+ TMG VTFET (d) Delta doped N+ GS TMG VTFET. We discovered that, out of the four configurations, the -doped n+ GS-TMG-VTEFT had the largest ON/OFF ratio and the best work function.  Additionally, these devices are employed as biosensors. We also performed analytical modelling of the suggested device with the surface potential characteristics and electrical field with drain current using the Kane model to validate the results.  The suggested gate stacked triple metal vertical TFET with n + delta doped layer (-doped n + SiGe GS-TMG-VTFET) uses a novel 2D analytical model to validate the surface potential, and a parabolic approximation approach is used to obtain the solution of the Poisson equation. The acquired value is characterised in terms of the electrical field and the channel surface potential, respectively. The planned technique contains of a dual modulation effect that is utilized to control the surface potential at the interfacing points of the source and drains along with the channel. This designed structure contains SiO2 and HfO2 as gate-stacked materials to increase the gate terminal control over the channel. With this gate stacked property, the proposed design TMG-VTFET beats the previous work regarding the surface potential and input & output characteristics ex. VGS & VDS, gate oxide, and SiGe mole fraction.  In conclusion, the work progresses to achieve the final expression of the channel surface potential, which includes the biasing variation of source and drain terminal. This proposed prototypical is accounting the variable of Kane model to obtain the drain current characteristics. This model can also be draft by integrating band-to-band tunneling generation rate using suitable boundary conditions. Finally, the different efficiency of the proposed model for the surface potential and for the drain current are validated and by demonstrating the agreement of the analytical results with the TCAD simulation results. Efficient realization of efficient XOR gate and some arithmetic and logical circuits. 1.2. Motivation New semiconductor technologies for both large power-performance and small-power implementations have been proposed like standard MOSFETs have proven inefficient in delivering the requisite performance in the nanoscale realm. We chose the tunnel field effect transistor (TFET) for technology innovation because it has a greater Ion/Ioff current ratio, a steeper subthreshold slope along with lower leakage current in comparison to the MOSFET. However, with ordinary TFETs, the phenomena of ‘band-to-band-tunnelling’ limits device’s drive current with scaling factor. As a result, a vertical approach of Tunnel FET with added smaller band gap material approaches has been investigated to overcome the aforementioned difficulties. This is further enhanced by the use of heterojunction, such as SiGe material, which reduces the tunnelling path required to improve the device. The phenomenon of band to band tunnelling, contrasted with restricts the final device's drive current with scaling factor in typical TFETs. As a result, to solve the aforementioned problems, a vertical Tunnel FET technique with added narrower band gap material approaches has been investigated. This is further strengthened by the use of heterojunction materials, such as SiGe, which decreases the tunnelling path wanted to progress the device. The TFETs are the weighted entity of this research. ‘Band-to-band-tunnelling’ which includes the movement of charge carriers by one energy band level to another energy band level, is the main injection mechanism, in comparison to MOSFETs, which thermally inject charge carriers through a potential barrier. In 1934, Zener made the first observation of this tunnelling mechanism. To achieve excellent characteristics of various structure researched in this field, various tedious task has been performed by the researchers to obtain parameters in certain range like steep SS value, high on current, low off current, greater on to off current value ratio, reduced average value of Sub threshold swing, low EDP and total energy consumed per operation in comparison to conventional devices available in this field before the evolution of T-FET. Achieving the highest ION, the lowest average SS across a wide range of drain currents, and the lowest IOFF are all objectives of TFET optimization. Due to the fact that SS in TFETs diminishes as gate voltage increases, they are ideally suited for low-voltage operation. In order to generate a strong tunnelling current and steep slope, the transfer probabilities of the tunneling barrier should be anywhere from zero to the really close to one for a small change in gate voltage close to the threshold potential. Incredibly thin channel barrier are needed, as well as significant channel band modulation by the gate. 1.3 Objective and Scope of Thesis  To mitigate the unwanted ambipolar conduction and optimized the work function at tunneling gate, control gate and auxiliary gate, to achieve Steeper SS, to extend the control of the gate terminal over the channel, to enhance the stability and sensitivity of the device.  To enhance the surface potential results in terms of input and output characteristics like gate-source voltage (VGS) and drain-source voltage (VDS), gate oxide, and SiGe mole fraction.  To design and performance assessment of heterojunction Vertical Tunnel FET for analyzing its electrical characteristics.  Parametric variation analysis of Vertical Tunnel FET for drive current enhancement using gate stacking method and triple metal gate combination.  Modeling and Simulation of proposed heterojunction Vertical Tunnel FET to evaluate and validate its surface potential characteristics.  The creation of a new channel surface potential expression that can predict the effect of source-channel and drain-channel both the biasing. The Kane's Model is used to calculate the drain current by measuring the band-to-band tunneling generation rate. To developed a new 2D analytical model of a triple metal Vertical TFET Gate stacked with n+ SiGe delta-doped layer using two-dimensional Poisson's equations.  To design and simulate the device for low power Bio-sensing application. 1.4 Thesis Organization The thesis is organized Chapter-wise, as outlined below: Chapter-1 The brief background and the basics of TFET, research objectives, contributions and motivation are discussed in this chapter. Chapter-2 It consists of the discussion of the theory and research methods with historical review of the different TFET structures. Chapter-3 Introduction of proposed design of Triple Metal Vertical TFET Gate Stacked with N-Type SiGe delta-doped layer and analysis of different TFET with and without presence of the gate stack and n+ δ-doped layer structures is performed. Chapter-4 It consists of the simulation and 2D analytical modeling of a new device of gate-stacked triple metal gate Vertical TFET with SiGe heterojunction delta doping layer. The proposed model is accounting the variable of Kane model in respect to extract the drain current characteristics. Chapter-5 Tunnel Field Effect Transistor (TFET) Based Biosensors for Biomedical field applications design and performance analysis. Chapter 6 Conclusion and Future Scope. 1.4. List of Publication Details of The Author • JOURNAL 1. Shilpi Gupta, Subodh Wairya, and Shailendra Singh. "Design and analysis of triple metal vertical TFET gate stacked with N-type SiGe delta-doped layer." Silicon 14.8 (2022): 4217-4225. doi:https://doi.org/10.1007/s12633-021-01211-3 2. Shilpi Gupta, Subodh Wairya, Shailendra Singh, “Analytical modeling and simulation of a triple metal vertical TFET with hetero-junction gate stack” Superlattices and Microstructures, Volume 157, 2021, 106992, ISSN 0749-6036, https://doi.org/10.1016/j.spmi.2021.106992. • BOOK CHAPTER 1. Singh, Jeetendra, Shilpi Gupta, and Balwinder Raj. "Shailendra Singh and Sanjeev Kumar Bhalla." Advanced Circuits and Systems for Healthcare and Security Applications (2022): 1. • INTERNATIONAL CONFERENCE 1. Gupta, Shilpi, Subodh Wairya, "Performance analysis of different Tunnel Field Effect Transistors (TFET) device structures with their Challenges", IEEE 8th International Conference on Signal Processing and Integrated Networks, SPIN-2021, organized by Amity University, Noida, IEEE, 2021, DOI : 10.1109/SPIN52536.2021.9566097. 2. Gupta, Shilpi, Subodh Wairya "Performance Estimation of Different Tunnel Field Effect Transistor Based Biosensors used in the Biomedical and its Future Prospective", 4th International Conference on VLSI, Communication & Signal Processing, Springer, Singapore, 2021.