The research focuses on two advanced TFET architectures:
Hetero-Dielectric Dual Source Vertical TFET (HDG-DS-VTFET)
Heterojunction Triple Metal Dual Gate Extended Source TFET (Hetero-TMDG-ES-TFET) Both are designed for ultra-low-power and high-frequency applications.
Enhanced Performance via TCAD Simulation Using SILVACO-ATLAS 2D simulations, the proposed devices show significant improvements in DC, RF, analog, and noise characteristics compared to conventional TFETs.
Key Benefits of HDG-DS-VTFET
Exhibits steep subthreshold slope (SS)
Shows reduced threshold voltage (Vth)
Achieves a high ION/IOFF ratio
Utilizes hetero-dielectric gate to improve tunneling efficiency and minimize leakage
Advantages of Hetero-TMDG-ES-TFET
Combines SiGe/Si heterojunction, extended source, and triple-metal gate
Demonstrates excellent linearity (VIP, IIP3, IMD3), noise performance, and transconductance (gm)
Achieves an ION/IOFF/ ratio of 9.1 × 10¹², ideal for analog/RF applications
Overall Impact and Future Potential
These device structures successfully address limitations of conventional TFETs
Offer strong potential for next-generation low-power, high-performance nanoelectronic circuits, including logic, RF, and mixed-signal domains
Content Owner / Guide
Title
Performance Investigation of Hetero-Dielectric and SiGe Heterojunction Gate Tunnel FET for Low Power Applications
Type
Doctor of Philosophy
Place of Work
E-Mail
Registration Date
Area of Research
Nano VLSI Design