Priyanka Pandey (1805267008)

Frequency divider requirements in modern wireless transmission systems are getting more and more stringent. These specifications are a result of the different radio standards that today's mobile devices must comply with. The challenge of constructing frequency dividers with multi-band functionality increases as a result of this multi-standard support. In this thesis, basically, an outline of a design approach for high frequency divider circuit is presented. Firstly, the thesis covers pass transistor logic, level restoring logic, cascaded NMOS, NMOS transistor in serial/parallel, different types of edge triggering flip flops, level triggering, their comparison, CMOS inverter, and various performance parameters like voltage scaling, power estimation, delay abbreviation. With these background knowledge, thesis proceeds with a proposal of some of the flip-flop circuits and frequency divider circuit. Flip flop circuits are designed through various techniques such as PTL, CMOS and GDI. CADENCE Virtuoso 16.1 GPDK version has been used for circuit design analysis. After simulation of the D flip flop circuit with the PTL technique, power consumption has been found to be reduced by 99.371% with the CMOS technique at 90nm technology, and it is reduced by 99.39% at 45nm technology, respectively. In this work; voltage analysis, temperature analysis, and comparative analysis with different flip flop circuits have been performed. To overcome the limitations of existing techniques, we have presented a GDI approach that helps for reducing power consumption, used only 1.123 μW. Further, we simulate a frequency divider circuit with GDI technique, which provides great features and performance than reported circuits. This consumes 1.927 μW average power and delay is 367.5 ps. Corner analysis and Monte-Carlo analysis have also been performed. To conclude, it can say that for low power consumption these techniques are efficient in every manner.