Jyoti Garg (PhD/15/ECE/2055)

1.1 Abstract The work carried out in this thesis is concerned with the design of electronic logic circuits using Spin Transfer Torque Magnetic Random Access Memory(STT MRAM), Spin Hall Effect(SHE) assisted STT-MRAM, Memristor. The thesis presents a detailed theory about STT-MRAM, SHE and Memristor. Several initial designs and implementations, available in literature, have been discussed for an in-depth understanding of the subject. It has been observed that here is a scope for designing and implementing new STT-MRAM and memristor based logic circuits and applications with improved circuit parameters like area, circuit complexity and clock delays. This form motivation to conduct the work carried out under this research program. It also presents in-depth study of non volatile memory circuits and summarizes various contemporary literatures available in this direction. The significance of conducting research on the topic of this thesis has been amply justified. CMOS Technology underpins all the aspects of information generation, storage, transformation, and transmission in the digital age. Moore’s law of scaling has aided in the development of information technology even today. Yet we are also getting close to the physical limits of Silicon as we approach the fundamental area, power and performance restrictions of the CMOS. Potential low power substitutes for CMOS technology that would go beyond CMOS are spintronics devices. The Magnetic Tunnel Junction (MTJ) based Spin transfer torque Magneto random access Memory (STT-MRAM) is considered to be the most practical spintronic component that can be used in the next- generation microprocessors system. The STT MRAM has shown some advantages over conventional SRAM based memory , including non volatility, 0% static power, and reduced bit cell size. The STT- MRAM is anticipated to perform better than the SRAM in higher level cache memory applications due to its shorter global interconnects. This thesis examines the use of these technologies beyond memory in terms of logic design, digital and analog application. For the various applications, We suggested a spintronics based logic in memory structure. The top contender for spin based memories is spin transer torue magneto resistive random access memory (STT-MRAM). In order to design the widely used AND, NAND, OR, NOR, XOR, XNOR gate, key aspects of MTJ, STT-MRAM are explored and utilised. All of these circuits are examined in terms of latency, area and power consumption. In addition to logic gates, a combinational circuit- full adder is attempted and assessed using the same criteria. This research is mainly concerned with methods of improving the performance of spntronics based logic and combinatorial circuitry that have been implemented using the proposed Spin Hall effect (SHE) assisted STT- MRAM. SHE assisted STT MRAM is an alternative to the STT-MRAM that offers non volatility, zero leakage and competitive area per bit with a lower write current. Logic Circuits- AND, NAND, OR, NOR, XOR, XNOR have been implemented using the key properties of SHE assisted STT MRAM. Combinational Circuit- Full adder and Arithmetic Logic Unit (ALU) is designed and evaluated in terms of power, area and latency. Till now , three fundamental circuit components known to date are the capcacitor, resistor and the inductor. The relationship between two of the four fundamental ciruit variables- current, voltage, charge and flux- defines these circuit components. In 1971, Professor Leon Chua suggested that there are should be a forth fundamental circuit element that provides the relationship between flux and charge on the basis of symmetry. He have it the name memristor , which stands for memory resistor. As a result , switching to new technology is urgently needed at both architecture and device level. Memristor structure have recently drawn interest as potential contender for this position.Memristor technology open up new possibilities for creating innovative circuit systems. Memristor is thought to be a good substitute option for CMOS technology’s scaling problem. Memristor usage in circuit design has grown significantly in recent years , sparking curiosity among researchers. The size and complexity of memristor designs have improved. Major issues with CMOS transistor development include leakage power, decreased reliability nd expensive fabrication- all have been deal with this single element. As Memristors have properties of non volatility, small size, capacity for long term data storage, low power consumption, and compatibility with CMOS, pinched hysteresis I-V curve, frequency dependence, considered a crucial component in the design of memory. In This thesis memristor and memristor model has been studied. This thesis mainly focus on the application of memristor. In this thesis, analog and digital memristor applications are proposed using a memristive emulator circuit that successfully simulates a memristor’s behavior without needing any complicated circuit component. In analog application- relaxation oscillator are implemented, where as logic gates- AND, NAND, OR, NOR, XOR, XNOR and combinational circuits- Full adder, Encoder, Decoder, Multiplexer are implemented in digital application. All the proposed circuits have a superior performance in terms of circuit parameters like area, complexity and energy consumption in comparison to the contemporary designs. Finally, the thesis presents a discussion on the work conducted. The results of computer simulation tests carried out on the proposed spintronics based circuits and systems have been summarized and presented. Scope for further research in the area of concern has also been discussed. The thesis concludes with a bibliography of literature consulted during the course of research conducted under this research program. • Some of the special contributions include in this thesis are as follows: As logical circuits are highly employable in various combinational and encryption circuits, the different technologies to implement these gates offer large scale improvements in parameters like power and speed. By reviewing thoroughly, the most suited structures of logical ciruits, combinational circuits may be identified. Using these designs, the following objectives are proposed to be addressed in the circuits.  Efficient realization of efficient logical circuits and Arithmetic Logic Unit (ALU).  Efficient realialization of logical ciruits using Magntic tunnel Junction (MTJ).  A better demonstration of Full Adder circuit using logical circuits (designed using MTJ).  Logic circuits have been designed using Spin Hall Effect (SHE) assisted Spin Transfer Torque (STT) and to anaylaze circuit paramers.  Reported Full adder (FA) circuit and Arithmatic Logic unit (ALU) using SHE assisted STT and compared with previous existing designs.  Logic circuits have been designed using Memristor emulator circuit to show memristor have less complexity.  Efficient realization of digital( Full adder, Decoder, Encoder and Multiplexer) and analog (Oscilliator) application of memristor. 1.2. Motivation The arms race between chip manufacturers to offer the newest and best to lure customers only gets more intense as technology becomes more pervasive in our lives. An unintended consequence of this expansion is a rising need for effectiveness and performance. CMOS transistors have traditionally been grown to smaller nodes to "fit in" more functionality while reducing the overall energy footprint of the operation to meet this issue. Unfortunately, it is getting harder to shrink transistors, which drastically diminishes the incentive for such an undertaking to be profitable. The demand for high-bandwidth computation and leakage power (in caches) are two additional difficulties that are emerging in integrated circuit (IC) design. Due to this foresight, the industry started looking into alternative memory technologies that could replace CMOS in cache applications while supplying non-volatility (to eradicate leakage), high-density (high-bandwidth compute), and high-endurance. These technologies included resistive RAM (RRAM), phase change RAM (PCRAM), spin transfer torque RAM (STTRAM), domain wall memory (DWM), magnetic RAM (MRAM), ferroelectric RAM (FeRAM), memristor etc. Using these new memory technologies has the unintended consequence of raising security, privacy, and counterfeiting concerns. As the need for technology grows, so will the incentive for opponents to tamper with it for financial, political, and social benefit. According to the International Technological Roadmap for Semiconductors, spintronic memory, which takes advantage of both the charge and, more crucially, the magnetic or spin of electrons, offers a significant perspective for the "beyond CMOS." Because to its great durability, retention, and density while functioning at low voltages, STTRAM and Memristor have a lot of potential. This inspired me to investigate different spintronic memory (STT-MRAM and SHE-STT MRAM) and memristor applications in both digital and analog applications. 1.3. Objective and Scope of Thesis  Some study on Spintronics based devices and circuits had been done prior to this thesis. Many logic circuits , arithmetic logic unit have been constructed earlier also. SRAM Cell , Flash Memory and MRAM was first studied to understand their functionality. MRAM(1T-1MTJ) , MRAM (4T-2MTJ) was studied and implemented and compared with SRAM and Flash Cell.  New potential designs using STT-MRAM(logic in memory approach) have been designed. These circuits have been designed with care to decrease space, circuit complexity, and clock delays. The proposed logic circuits (AND, NAND, OR, NOR, XOR, XNOR) performance is compared with conventional CMOS logic circuits in terms of Power and latency. These proposed circuits can be beneficial in many digital circuits.  New potential logic designs using SHE assisted STT-MRAM (logic in memory approach) have been designed. These circuits have been designed with care to decrease space, circuit complexity, and clock delays. The proposed logic circuits (AND, NAND, OR, NOR, XOR, XNOR) performance is compared with conventional CMOS logic circuits in terms of Power and latency. The simulation results obtained with the Cadence Virtuoso validate the proposed circuit's right functioning.  An Arithmatic Logic unit (ALU) is designed using Proposed logic circuits (SHE Assisted STT) in this thesis and have been evaluated and compared in terms of Power, Latency and area. ALU is a important element of memory and can be used in application of memory.  Another important Memory Technology- Memristor is studied in this thesis. Logic ciruits (AND, NAND, OR, NOR, XOR, XNOR) have been proposed using memristor emulator circuits and compared with conventional CMOS logic circuits in terms of power, area, latency and power delay product.  Digital(Full Adder, Decoder, Encoder and Multiplexer) and Analog applications (Oscillator) of Proposed logic circuits using memristor have also presented in this thesis. The proposed arithmetic circuits have superior performance in terms of circuit parameters like area, complexity and power consumption in comparison to the conventional approaches. 1.4. Thesis Organization The thesis is organized Chapter-wise, as outlined below: Chapter-1 The brief background and the basics of Non Volatile Memory, research objectives, contributions and motivation are discussed in this chapter. Chapter-2 It consists of literature review and state of the art work. Chapter-3 Introduction of STT- MRAM based proposed logic gates and Full adder circuit, their implementation and comparison. Chapter-4 Introduction of Arithmetic Logic Unit (ALU) using Spin Hall Effect (SHE) assisted STT- MRAM. To Design ALU, Logic circuits have been proposed using SHE assisted STT MRAM. Chapter-5 It Introduction of Memristor based Logic circuit and their digital and analog application. Chapter 6 Conclusion and Future Scope. 1.5. List of Publication Details of The Author • JOURNAL (Scopus Index) 1. Jyoti Garg, Niharika Varshney and Subodh Wairya, Comparative study of Magnetic Tunnel Junction based 4 T - MRAM, International Journal of Advanced Research in Engineering and Technology (IJARET), 11(5), 2020, pp. 1178-1186. https://iaeme.com/Home/article_id/IJARET_11_05_128 2. Garg, Jyoti & Wairya, Subodh. (2022). Performance Evaluation of Low Power Hybrid Combinational Circuits using Memristor. International Journal of Electrical and Electronics Research. http://doi.org/10. 988-993. 10.37391/ijeer.100439. 3. Jyoti Garg, Subodh Wairya, “Design of Low Power Arithmetic logic unit using SHE assisted STT / MTJ”,International Journal of Computing and Digital Systems, vol 13 issue 1, pp 190-197, ISSN: 2210-142X. /https://journal.uob.edu.bh/bitstream/ handle/123456789/4865/1570818159.pdf. • BOOK CHAPTER (Scopus Index) 1. Garg J., Wairya S. (2021) Performance Evaluation of Logic Gates Using Magnetic Tunnel Junction. In: Gopi E.S. (eds) Machine Learning, Deep Learning and Computational Intelligence for Wireless Communication. Lecture Notes in Electrical Engineering, vol 749. Springer, Singapore, pp 313–321, ISBN 978-981-16-0289-4, https://doi.org/10.1007/978-981-16-0289-4_23. (Scopus Indexed) 2. Garg, J., Wairya, S. (2022). STT-MRAM A Universal Memory from Device to Circuit. In: Bansal, R.C., Agarwal, A., Jadoun, V.K. (eds) Advances in Energy Technology. Lecture Notes in Electrical Engineering, vol 766. Springer, Singapore, pp 673-681, ISBN 978-981-16-1476-7, https://doi.org/10.1007/978-981-16-1476-7_60. (Scopus Indexed) 3. Garg, J., Wairya, S. (2022). Performance Evaluation of Full Adder Using Magnetic Tunnel Junction. In: Mahapatra, R.P., Peddoju, S.K., Roy, S., Parwekar, P., Goel, L. (eds) Proceedings of International Conference on Recent Trends in Computing . Lecture Notes in Networks and Systems, vol 341. Springer, Singapore, pp 517–526, ISBN 978-981-16-7118-0, https://doi.org/10.1007/978-981-16-7118-0_44. (Scopus Indexed) 4. Semba Walli, Jyoti Garg, Subodh Wairya, “Analog and Digital Applications of 4-T Based Memristor Emulator ”, International Conference On VLSI & Microwave and Wireless Technologies (ICVMWT-2021), MMMTU, Gorakhpur, India, 20-21 March. 2021. Lecture Notes in Electrical Engineering , 877, VLSI, Microwave and Wireless Technologies: Select Proceedings of ICVMWT 2021, pp. 183-194, ISSN 1876-1119, ISBN 978-981-1903113, http://doi.org/10.1007/978-981-19-0312-0. (Scopus Indexed) 5. Jyoti Garg, Aishita Verma, Subodh Wairya “ Memristor Emulator Circuits an Emerging Technology with Applications ”, International Conference On VLSI & Microwave and Wireless Technologies (ICVMWT-2021) , MMMTU, Gorakhpur, India, 20-21 March. 2021. Lecture Notes in Electrical Engineering , 877, VLSI, Microwave and Wireless Technologies: Select Proceedings of ICVMWT 2021, pp. 467-480, ISSN 1876-1119, ISBN 978-981-1903113, http://doi.org/10.1007/978-981-19-0312-0. (Scopus Indexed)