PERFORMANCE AND DESIGN ANALYSIS OF TERNARY ARITHMETIC LOGIC CIRCUITS
Content Owner / Guide
Subodh Wairya
Title
PERFORMANCE AND DESIGN ANALYSIS OF TERNARY ARITHMETIC LOGIC CIRCUITS
Year Awarded (Blank if Not Awarded)
2023
Awarding Body
IET Lucknow
Type
Master of Technology
Place of Work
IET Lucknow
E-Mail
[email protected]
Related Department
Electronics & Communication Engineering Department
Roll No
2100521195006
Registration Date
Area of Research
Digital Logic design for high speed VLSI application