Dr APJ Abdul Kalam Technical University Uttar Pradesh, Lucknow

The majority of full adder (FA) circuits are implemented employing three separate modules in a hybrid logic architecture. The main distinguishing feature of these hybrid logic style-based FA cells is that each module can be individually adjusted to increase circuit performance. With pass, a high-performance 1-bit hybrid FA cell is presented. In this paper, transistor logic and transmission gate logic are used. The proposed FA circuit is realized with the help of to get the best results, you'll need 20 transistors.

The development of manufacturers and designers is looking the methods for conventional smaller-sized and high-performance devices with the circuit reduced the power consumption and enhanced the gain margin, phase margin is the most important parameter of an operational transconductance amplifier (OTAs). Which have become essential building blocks of many modern analogy and mixed–the signal circuit is used as a key element in a wide variety of circuits that benefit from voltage control.

Accuracy Configurable Adder (ACA) is 28.36% faster and consumes 30.11% less power than Ripple Carry Adder (RCA). Power Delay Product (PDP) is the figure of merit for digital logic circuits. The less is the value of PDP, the more Energy-efficient is circuit. ACA provides 47% less PDP and 62% less Energy Delay Product (EDP) as compared to RCA.

Barrel shifter is a elementary block of numerous computing systems due to its operation that it can shift and rotate multiple bits in one cycle. The barrel shifter can replace arithmetic and the logical shifters as it uses the rotation of the data. In 2018 Barrel shifters were designed using Adiabatic logic. Adiabatic logic is one of the common technique used to minimize energy loss and it can be used in analog as well as digital logic design.

The major challenge in orthogonal frequency division multiplexing (OFDM) is to reduce high peak to average power ratio (PAPR) that leads to non linear distortion for the application of high power amplifier. PAPR is defined as the ratio between the maximum instantaneous power and its average power. In this paper, we have presented new PAPR reduction technique to reduce peak to average power ratio using Linear predicting coding (LPC) in OFDM system.

Sense amplifier plays an important role in semiconductor memories which used to sense the stored data in memory cell. Two most important parameters like sensing delay and voltage are used in sense amplifier. Sense amplifier reduces the overall sensing delay and voltage. Voltage mode sense amplifier detects the voltage difference between bit-line and bit-line bar but when increases the memory size the bit-line and bit-line capacitance also increases. In this paper all circuit design analysis using Tanner 14.1 version simulation tool at 1.5v/45nm CMOS Technology.