VLSI Design Lab

Incharge
Dr Subodh Wairya
Lab Area:510 Sqfeet
Room Number: EC 316

Lab Faculty: Er Anum Khan

Lab Assistant: Mr PK Bhattacharya

Lab Staff: Mr Jai Krishan Tiwari

 Number of PCs: 10

Courses Covered

  • REC 851/ EC 851-Project Lab
  • REC 752/ EC 752-Electronics Circuit Design Lab

List of Experiments

REC 752: ELECTRONICS AND CIRCUIT DESIGNING LAB
Experiments using CADENCE VIRTUOSO
1. CMOS Inverter :
a) Design and verify the circuit (using 180 nm techonology) using transient
analysis.
b) Obtain VTC curve and threshold voltage of inverter for a specific parameter,
verify with the value of threshold voltage obtained using formula.
c) Create symbol of this inverter for further application.
2. Design NAND and NOR gate using 180 nm technology perform all the
analysis using cadence virtuoso.
3. Design XOR gate by using NAND and NOR gate. Perform transient
analysis.
4. Design 1-bit half adder using 90 nm technology and verify the circuit using
transient analysis.
5. Design Full adder using 90 nm technology and verify the circuit using
transient analysis.
6. Design a multiplexer using 90 nm technology and perform all the analysis to
verify its characteristics.
7. Design a MOS based SRAM cell using 90 nm technology and verify its
characteristics.
8. Design NOR gate using Domino logic CMOS inverter and verify its
characteristics.
9. Design CMOS transmission gate and perform all the analysis to verify its
characteristics.
10. Design XOR and XNOR gate using dynamic CMOS logic circuits and verify
its characteristics.
11. Design Layout of CMOS inverter and perform post layout analysis, Monte
Carlo analysis, Corner analysis and etc.

Facilities/Softwares Available:

  • Software Xilinx ISE System Edition  16.4
  • Microwind 3.5 package
  • System Crafter SC Version
  • Advance VLSI Proto Board
  • Xilinx Spartan ® 6FPGA
  • Xilinx Virtex ® Board with aerial Ethernet cable of 5 V Power supply
  • CPLD(Xilinx Xc 95108PC84) Development Board
  • Cadence Virtuoso 6.1.7  (10 user)